View D789477_4609565.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

user?s manual pD789477 pd789478 pd789479 pd78f9478 pd78f9479 pd789478 subseries 8-bit single-chip microcontrollers printed in japan document no. u15400ej3v0ud00 (3rd edition) date published may 2003 n cp(k) ? 2001 www.datasheet.co.kr datasheet pdf - http://www..net/
2 user?s manual u15400ej3v0ud [memo] www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom and fip are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. www.datasheet.co.kr datasheet pdf - http://www..net/
4 user ? s manual u15400ej3v0ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of december, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec e lectronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec e lectronics" as used in this statement means nec e lectronics c orporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": www.datasheet.co.kr datasheet pdf - http://www..net/
user ? s manual u15400ej3v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa ? a madrid, spain tel: 091-504 27 87 v lizy-villacoublay, france tel: 01-30-67 58 00 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: www.datasheet.co.kr datasheet pdf - http://www..net/
6 user?s manual u15400ej3v0ud major revisions in this edition page description throughout ? addition of pd789479 and 78f9479 ? addition of 80-pin plastic tqfp (fine pitch) (12 x 12) p.29 chapter 1 general ? update of series lineup diagram in 1.5 78k/0s series lineup p.52 chapter 3 cpu architecture ? addition of table 3-3 internal high-speed ram, internal low-speed ram capacity pp.98, 104, 105 chapter 5 clock generator ? modification of description of minimum instruction execution time in figure 5-3. format of processor clock control register and figure 5-5. format of subclock control register ? addition of 5.4.6 subsystem clock 4 multiplication circuit p.118 chapter 6 16-bit timer 20 ? addition of 6.5 cautions on using 16-bit timer 20 pp.253, 265 chapter 13 lcd controller/driver ? modification of figure 13-2 lcd controller/driver block diagram ? addition of 13.8 examples of lcd drive power connections p.289 chapter 16 interrupt functions ? addition of description of key return mode register 01 (krm01) pp.319, 320 chapter 19 flash memory version ? modification of description of cpu clock in table 19-2 communication mode list ? change of description of note 1 in figure 19-3 example of connection with dedicated flash programmer p.357 addition of chapter 23 electrical specifications (target) ( pd789479, 78f9479) pp.380, 381 appendix a development tools ? addition of flashpro iv and fa-80gk-9eu to a.4 flash memory writing tools ? modification of a.5 debugging tools (hardware) p.383 addition of appendix b notes on target system design the mark shows major revised points. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 7 introduction target readers this manual is intended for user engineers who wish to understand the functions of the pd789478 subseries and design and develop application systems and programs using these devices. target products: ? pd789478 subseries: pD789477, 789478, 789479, 78f9478, 78f9479 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization two manuals are available for the pd789478 subseries: this manual and the instruction manual (common to the 78k/0s series). pd789478 subseries user?s manual 78k/0s series instructions user?s manual ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to understand the overall functions of the pd789478 subseries read this manual in the order of the contents . ? how to read register formats the name of the bit whose number is in angle brackets (<>) is reserved in the assembler and is defined by the header file sfrbit.h in the c compiler. ? to learn the detailed functions of a register whose register name is known see appendix c register index . ? to learn the details of the instruction functions of the 78k/0s series refer to 78k/0s series instructions user?s manual (u11047e) separately available. ? to learn about the electrical specifications of the pd789478 subseries refer to chapter 22 electrical specifications ( pD789477, 789478, 78f9478) and chapter 23 electrical specifications (target) ( pd789479, 78f9479) . www.datasheet.co.kr datasheet pdf - http://www..net/
8 user?s manual u15400ej3v0ud conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789478 subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to development tools (software) (user?s manuals) document name document no. operation u14876e language u14877e ra78k0s assembler package structured assembly language u11623e operation u14871e cc78k0s c compiler language u14872e operation (windows ? based) u15373e sm78k series system simulator ver. 2.30 or later external part user open interface specifications u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e project manager ver. 3.12 or later (windows based) u14610e documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789488-ns-em1 emulation board to be prepared documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user's manual u13502e pg-fp4 flash memory programmer user's manual u15260e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 9 other related documents document name document no. semiconductor selection guide - products & packages - (cd-rom) x13769e semiconductor device mounting technology manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webpage (http://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. www.datasheet.co.kr datasheet pdf - http://www..net/
10 user?s manual u15400ej3v0ud contents chapter 1 general........................................................................................................... ................24 1.1 features .................................................................................................................. ....................24 1.2 applications.............................................................................................................. ..................24 1.3 ordering information ...................................................................................................... ...........25 1.4 pin configuration (top view).............................................................................................. ......26 1.5 78k/0s series lineup...................................................................................................... ...........29 1.6 block diagram ............................................................................................................. ...............32 1.7 overview of functions..................................................................................................... ..........33 chapter 2 pin functions .................................................................................................... ...........35 2.1 list of pin functions..................................................................................................... .............35 2.2 description of pin functions .............................................................................................. ......38 2.2.1 p00 to p07 (port 0) ..................................................................................................... .................. 38 2.2.2 p10, p11 (port 1) ....................................................................................................... ................... 38 2.2.3 p20 to p25 (port 2) ..................................................................................................... .................. 38 2.2.4 p30 to p34 (port 3) ..................................................................................................... .................. 39 2.2.5 p50 to p53 (port 5) ..................................................................................................... .................. 39 2.2.6 p60 to p67 (port 6) ..................................................................................................... .................. 40 2.2.7 p70 to p73 (port 7) ..................................................................................................... .................. 40 2.2.8 p80 to p87 (port 8) ..................................................................................................... .................. 40 2.2.9 s0 to s27 ............................................................................................................... ....................... 40 2.2.10 com0 to com3 ........................................................................................................... ................. 40 2.2.11 v lc0 to v lc2 ............................................................................................................................... .... 40 2.2.12 nc..................................................................................................................... ............................ 40 2.2.13 reset .................................................................................................................. ........................ 40 2.2.14 x1, x2 ................................................................................................................. .......................... 41 2.2.15 xt1, xt2............................................................................................................... ........................ 41 2.2.16 av dd ............................................................................................................................... ............... 41 2.2.17 av ss ............................................................................................................................... ............... 41 2.2.18 v dd ............................................................................................................................... ................. 41 2.2.19 v ss ............................................................................................................................... ................. 41 2.2.20 v pp (flash memory only) ........................................................................................................... ..... 41 2.2.21 ic0 (mask rom version only) ............................................................................................ ........... 41 2.3 pin i/o circuits and recommended connection of unused pins .........................................42 chapter 3 cpu architecture ................................................................................................. .....46 3.1 memory space .............................................................................................................. ..............46 3.1.1 internal program memory space ........................................................................................... ........ 51 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 11 3.1.2 internal data memory space .............................................................................................. ........... 52 3.1.3 special function register (sfr) area.................................................................................... ......... 52 3.1.4 data memory addressing.................................................................................................. ............ 53 3.2 processor registers ....................................................................................................... ........... 58 3.2.1 control registers ....................................................................................................... .................... 58 3.2.2 general-purpose registers ............................................................................................... ............. 61 3.2.3 special function registers (sfrs) ....................................................................................... .......... 62 3.3 instruction address addressing ............................................................................................ .. 66 3.3.1 relative addressing ..................................................................................................... ................. 66 3.3.2 immediate addressing .................................................................................................... .............. 67 3.3.3 table indirect addressing............................................................................................... ............... 68 3.3.4 register addressing..................................................................................................... ................. 68 3.4 operand address addressing ................................................................................................ .. 69 3.4.1 direct addressing....................................................................................................... ................... 69 3.4.2 short direct addressing................................................................................................. ................ 70 3.4.3 special function register (sfr) addressing .............................................................................. .... 71 3.4.4 register addressing..................................................................................................... ................. 72 3.4.5 register indirect addressing ............................................................................................ ............. 73 3.4.6 based addressing ........................................................................................................ ................. 74 3.4.7 stack addressing ........................................................................................................ .................. 74 chapter 4 port functions ................................................................................................... ........ 75 4.1 port functions............................................................................................................ ................ 75 4.2 port configuration ........................................................................................................ ............. 76 4.2.1 port 0 .................................................................................................................. .......................... 77 4.2.2 port 1 .................................................................................................................. .......................... 78 4.2.3 port 2 .................................................................................................................. .......................... 79 4.2.4 port 3 .................................................................................................................. .......................... 84 4.2.5 port 5 .................................................................................................................. .......................... 86 4.2.6 port 6 .................................................................................................................. .......................... 87 4.2.7 port 7 .................................................................................................................. .......................... 89 4.2.8 port 8 .................................................................................................................. .......................... 90 4.3 registers controlling port function ....................................................................................... .91 4.4 port function operation................................................................................................... ......... 94 4.4.1 writing to i/o port..................................................................................................... ..................... 94 4.4.2 reading from i/o port ................................................................................................... ................ 94 4.4.3 arithmetic operation of i/o port ........................................................................................ ............. 94 chapter 5 clock generator .................................................................................................. .... 95 5.1 clock generator functions................................................................................................. ...... 95 5.2 clock generator configuration ............................................................................................. ... 95 5.3 registers controlling clock generator ................................................................................... 98 5.4 system clock oscillators .................................................................................................. ...... 101 5.4.1 main system clock oscillator ............................................................................................ ........... 101 www.datasheet.co.kr datasheet pdf - http://www..net/
12 user?s manual u15400ej3v0ud 5.4.2 subsystem clock oscillator.............................................................................................. ............ 102 5.4.3 example of incorrect resonator connection............................................................................... .. 103 5.4.4 divider circuit ......................................................................................................... ..................... 104 5.4.5 when no subsystem clock is used......................................................................................... ..... 104 5.4.6 subsystem clock 4 multiplication circuit................................................................................... 104 5.5 clock generator operation ................................................................................................. ....105 5.6 changing setting of system clock and cpu clock..............................................................106 5.6.1 time required for switching between system clock and cpu clock............................................ 106 5.6.2 switching between system clock and cpu clock........................................................................ 107 chapter 6 16-bit timer 20 ................................................................................................. ...........108 6.1 16-bit timer 20 functions ................................................................................................. ......108 6.2 16-bit timer 20 configuration............................................................................................. ....108 6.3 registers controlling 16-bit timer 20....................................................................................1 10 6.4 16-bit timer 20 operation ................................................................................................. ......113 6.4.1 operation as timer interrupt ............................................................................................ ............ 113 6.4.2 operation as timer output ............................................................................................... ............ 115 6.4.3 capture operation ....................................................................................................... ................ 116 6.4.4 16-bit timer counter 20 readout......................................................................................... .......... 117 6.5 cautions on using 16-bit timer 20......................................................................................... 118 6.5.1 restrictions when rewriting 16-bit compare register 20 .............................................................. 118 chapter 7 8-bit timers 50, 60, and 61 .................................................................................. ..120 7.1 functions of 8-bit timers 50, 60, and 61 ...............................................................................120 7.2 configuration of 8-bit timers 50, 60, and 61 .........................................................................122 7.3 control registers for 8-bit timers 50, 60, and 61 .................................................................128 7.4 operation of 8-bit timers 50, 60, and 61................................................................................13 4 7.4.1 operation as 8-bit timer counter ........................................................................................ ......... 134 7.4.2 operation as 16-bit timer counter ....................................................................................... ........ 143 7.4.3 operation as carrier generator.......................................................................................... .......... 149 7.4.4 pwm free-running mode operation (timer 50)............................................................................. 1 53 7.4.5 operation as pwm pulse generator (timer 60 and timer 61) ...................................................... 157 7.5 cautions on using 8-bit timers 50, 60, and 61 .....................................................................160 chapter 8 watch timer...................................................................................................... ..........161 8.1 watch timer functions ..................................................................................................... ......161 8.2 watch timer configuration ................................................................................................. ....162 8.3 control registers for watch timer......................................................................................... 163 8.4 watch timer operation..................................................................................................... .......165 8.4.1 operation as watch timer ................................................................................................ ............ 165 8.4.2 operation as interval timer............................................................................................. ............. 165 chapter 9 watchdog timer................................................................................................... .....167 9.1 watchdog timer functions.................................................................................................. ...167 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 13 9.2 watchdog timer configuration .............................................................................................. 168 9.3 watchdog timer control registers........................................................................................ 16 9 9.4 watchdog timer operation .................................................................................................. ... 171 9.4.1 operation as watchdog timer ............................................................................................. ......... 171 9.4.2 operation as interval timer............................................................................................. ............. 172 chapter 10 8-bit a/d converter ............................................................................................ .. 173 10.1 8-bit a/d converter functions............................................................................................ .... 173 10.2 8-bit a/d converter configuration ........................................................................................ . 173 10.3 8-bit a/d converter control registers................................................................................... 1 76 10.4 8-bit a/d converter operation ............................................................................................ .... 179 10.4.1 basic operation of 8-bit a/d converter ................................................................................. ....... 179 10.4.2 input voltage and conversion result .................................................................................... ........ 180 10.4.3 operation mode of 8-bit a/d converter .................................................................................. ..... 182 10.5 cautions related to 8-bit a/d converter ............................................................................... 183 chapter 11 serial interface 20 ............................................................................................ .. 187 11.1 serial interface 20 functions ............................................................................................ ...... 187 11.2 serial interface 20 configuration........................................................................................ .... 187 11.3 serial interface 20 control registers .................................................................................... . 191 11.4 serial interface 20 operation ............................................................................................ ...... 198 11.4.1 operation stop mode .................................................................................................... .............. 198 11.4.2 asynchronous serial interface (uart) mode.............................................................................. 200 11.4.3 3-wire serial i/o mode................................................................................................. ................ 212 chapter 12 serial interface 1a0........................................................................................... . 217 12.1 function of serial interface 1a0 ......................................................................................... .... 217 12.2 configuration of serial interface 1a0.................................................................................... . 217 12.3 control registers for serial interface 1a0............................................................................. 22 0 12.4 serial interface 1a0 operation........................................................................................... ..... 225 12.4.1 operation stop mode .................................................................................................... .............. 225 12.4.2 3-wire serial i/o mode................................................................................................. ................ 226 12.4.3 3-wire serial i/o mode with automatic transmit/receive function................................................. 231 chapter 13 lcd controller/driver ....................................................................................... 251 13.1 lcd controller/driver functions.......................................................................................... .. 251 13.2 lcd controller/driver configuration ..................................................................................... 2 51 13.3 registers controlling lcd controller/driver ........................................................................ 254 13.4 setting lcd controller/driver ............................................................................................ ..... 256 13.5 lcd display data memory .................................................................................................. .... 256 13.6 common and segment signals .............................................................................................. 2 57 13.7 display modes ............................................................................................................ .............. 259 13.7.1 three-time-slice display example ....................................................................................... ........ 259 13.7.2 four-time-slice display example ........................................................................................ ......... 262 www.datasheet.co.kr datasheet pdf - http://www..net/
14 user?s manual u15400ej3v0ud 13.8 example of lcd drive power connections ...........................................................................265 chapter 14 multiplier....................................................................................................... ............266 14.1 multiplier function ...................................................................................................... .............266 14.2 multiplier configuration................................................................................................. ..........266 14.3 multiplier control register .............................................................................................. ........268 14.4 multiplier operation ..................................................................................................... ............269 chapter 15 remote controller receiver .........................................................................270 15.1 remote controller receiver functions..................................................................................270 15.2 remote controller receiver configuration ...........................................................................270 15.3 registers to control remote controller receiver ................................................................276 15.4 operation of remote controller receiver .............................................................................278 15.4.1 format of type a reception mode........................................................................................ ........ 278 15.4.2 operation flow of type a reception mode................................................................................ .... 278 15.4.3 timing ................................................................................................................. ........................ 280 15.4.4 compare register setting............................................................................................... .............. 282 15.4.5 error interrupt generation timing ...................................................................................... ........... 284 15.4.6 noise elimination...................................................................................................... ................... 286 chapter 16 interrupt functions............................................................................................. 289 16.1 interrupt function types................................................................................................. ........289 16.2 interrupt sources and configuration .....................................................................................2 89 16.3 registers controlling interrupt function...............................................................................29 2 16.4 interrupt servicing operation ............................................................................................ .....299 16.4.1 non-maskable interrupt request acknowledgment operation...................................................... 299 16.4.2 maskable interrupt request acknowledgment operation ............................................................. 301 16.4.3 multiple interrupt servicing ........................................................................................... ............... 302 16.4.4 putting interrupt requests on hold ..................................................................................... .......... 304 chapter 17 standby function ................................................................................................ ..305 17.1 standby function and configuration.....................................................................................30 5 17.1.1 standby function ....................................................................................................... .................. 305 17.1.2 register controlling standby function .................................................................................. ........ 306 17.2 standby function operation............................................................................................... ....307 17.2.1 halt mode.............................................................................................................. ................... 307 17.2.2 stop mode .............................................................................................................. .................. 310 chapter 18 reset function.................................................................................................. ......313 chapter 19 flash memory version ........................................................................................317 19.1 flash memory characteristics ............................................................................................. ...318 19.1.1 programming environment................................................................................................ .......... 318 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 15 19.1.2 communication mode ..................................................................................................... ............ 319 19.1.3 on-board pin processing ................................................................................................ ............ 322 19.1.4 connection of adapter for flash writing ................................................................................ ....... 325 19.2 cautions on pd78f9478 and 78f9479 ................................................................................. 328 chapter 20 mask options .................................................................................................... ....... 329 chapter 21 instruction set................................................................................................. ...... 330 21.1 operation ................................................................................................................ .................. 330 21.1.1 operand identifiers and description methods ............................................................................ . 330 21.1.2 description of ?operation? column ...................................................................................... ........ 331 21.1.3 description of ?flag? column........................................................................................... ............ 331 21.2 operation list........................................................................................................... ................ 332 21.3 instructions listed by addressing type ............................................................................... 337 chapter 22 electrical specifications ( pD789477, 789478, 78f9478) ............................ 340 chapter 23 electrical specifications (target) ( pd789479, 78f9479) ........................ 357 chapter 24 package drawing................................................................................................. .. 374 chapter 25 recommended soldering conditions ........................................................... 376 appendix a development tools............................................................................................... 377 a.1 software package .......................................................................................................... .......... 379 a.2 language processing software ............................................................................................. 3 79 a.3 control software .......................................................................................................... ............ 380 a.4 flash memory writing tools ................................................................................................ ... 380 a.5 debugging tools (hardware)................................................................................................ .. 381 a.6 debugging tools (software) ................................................................................................ ... 382 appendix b cautions on designing target system ...................................................... 383 appendix c register index .................................................................................................. ....... 387 c.1 register index (alphabetic order of register name) ........................................................... 387 c.2 register index (alphabetic order of register symbol)........................................................ 390 appendix d revision history ................................................................................................ ..... 393 www.datasheet.co.kr datasheet pdf - http://www..net/
16 user?s manual u15400ej3v0ud list of figures (1/6) figure no. title page 2-1 i/o circuit types......................................................................................................... ................................... 44 3-1 memory map ( pD789477) ...................................................................................................................... ..... 46 3-2 memory map ( pd789478) ...................................................................................................................... ..... 47 3-3 memory map ( pd78f9478) ..................................................................................................................... .... 48 3-4 memory map ( pd789479) ...................................................................................................................... ..... 49 3-5 memory map ( pd78f9479) ..................................................................................................................... .... 50 3-6 data memory addressing ( pD789477)........................................................................................................ 53 3-7 data memory addressing ( pd789478)........................................................................................................ 54 3-8 data memory addressing ( pd78f9478)...................................................................................................... 55 3-9 data memory addressing ( pd789479)........................................................................................................ 56 3-10 data memory addressing ( pd78f9479)...................................................................................................... 57 3-11 program counter configuration............................................................................................ ......................... 58 3-12 program status word configuration........................................................................................ ...................... 58 3-13 stack pointer configuration.............................................................................................. ............................. 60 3-14 data to be saved to stack memory......................................................................................... ...................... 60 3-15 data to be restored from stack memory .................................................................................... .................. 60 3-16 general-purpose register configuration................................................................................... .................... 61 4-1 port types ................................................................................................................ ..................................... 75 4-2 block diagram of p00 to p07............................................................................................... .......................... 77 4-3 block diagram of p10 and p11.............................................................................................. ........................ 78 4-4 block diagram of p20 ...................................................................................................... .............................. 79 4-5 block diagram of p21 ...................................................................................................... .............................. 80 4-6 block diagram of p22 and p25.............................................................................................. ........................ 81 4-7 block diagram of p23 ...................................................................................................... .............................. 82 4-8 block diagram of p24 ...................................................................................................... .............................. 83 4-9 block diagram of p30 to p33............................................................................................... .......................... 84 4-10 block diagram of p34 ..................................................................................................... ............................... 85 4-11 block diagram of p50 to p53.............................................................................................. ........................... 86 4-12 block diagram of p60 to p67.............................................................................................. ........................... 87 4-13 block diagram of p70 to p73.............................................................................................. ........................... 89 4-14 block diagram of p80 to p87.............................................................................................. ........................... 90 4-15 port mode register format ................................................................................................ ........................... 91 4-16 format of pull-up resistor option registers.............................................................................. ................... 93 4-17 port function register format............................................................................................ ........................... 93 5-1 clock generator block diagram ( pD789477, 789478, and 789479)........................................................... 96 5-2 clock generator block diagram ( pd78f9478, 78f9479) ........................................................................... 97 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 17 list of figures (2/6) figure no. title page 5-3 format of processor clock control register ................................................................................ ..................98 5-4 format of subclock oscillation mode register.............................................................................. .................99 5-5 format of subclock control register....................................................................................... .....................100 5-6 format of subclock selection register ..................................................................................... ...................100 5-7 external circuit of main system clock oscillator .......................................................................... ...............101 5-8 external circuit of subsystem clock oscillator ............................................................................ ................102 5-9 examples of incorrect resonator connection ................................................................................ ..............103 5-10 switching between system clock and cpu clock............................................................................. ..........107 6-1 block diagram of 16-bit timer 20.......................................................................................... .......................109 6-2 format of 16-bit timer mode control register 20........................................................................... .............111 6-3 format of port mode register 3 ............................................................................................ .......................112 6-4 settings of 16-bit timer mode control register 20 for timer interrupt operation........................................113 6-5 timing of timer interrupt operation ....................................................................................... ......................114 6-6 settings of 16-bit timer mode control register 20 for timer output operation ..........................................115 6-7 timer output timing....................................................................................................... ..............................115 6-8 settings of 16-bit timer mode control register 20 for capture operation ..................................................1 16 6-9 capture operation timing (both edges of cpt20 pin are specified).......................................................... 116 6-10 16-bit timer counter 20 readout timing................................................................................... ..................117 7-1 block diagram of 24-bit event counter..................................................................................... ...................121 7-2 block diagram of timer 50 ................................................................................................. ..........................123 7-3 block diagram of timer 60 ................................................................................................. ..........................124 7-4 block diagram of timer 61 ................................................................................................. ..........................125 7-5 block diagram of output controller (timer 60) ............................................................................. ...............126 7-6 format of 8-bit timer mode control register 50............................................................................. .............128 7-7 format of 8-bit timer mode control register 60............................................................................ ..............130 7-8 format of carrier generator output control register 60 .................................................................... .........131 7-9 format of 8-bit timer mode control register 61............................................................................ ..............132 7-10 format of port mode register 3 ........................................................................................... ........................133 7-11 timing of interval timer operation with 8-bit resolution (basic operation) ............................................... .136 7-12 timing of interval timer operation with 8-bit resolution (when crnm is set to 00h)................................136 7-13 timing of interval timer operation with 8-bit resolution (when crnm is set to ffh) ...............................137 7-14 timing of interval timer operation with 8-bit resolution (when crnm changes from n to m (n < m)) .....137 7-15 timing of interval timer operation with 8-bit resolution (when crnm changes from n to m (n > m)) .....138 7-16 timing of interval timer operation with 8-bit resolution (when timer 60 match signal is selected for timer 50 count clock) .........................................................139 7-17 timing of operation of external event counter with 8-bit resolution ...................................................... ....140 7-18 timing of square-wave output with 8-bit resolution ....................................................................... ...........142 www.datasheet.co.kr datasheet pdf - http://www..net/
18 user?s manual u15400ej3v0ud list of figures (3/6) figure no. title page 7-19 timing of interval timer operation with 16-bit resolution ................................................................ .......... 144 7-20 timing of external event counter operation with 16-bit resolution ........................................................ ... 146 7-21 timing of square-wave output with 16-bit resolution ...................................................................... ......... 148 7-22 timing of carrier generator operation (when cr60 = n, crh60 = m (m > n))......................................... 150 7-23 timing of carrier generator operation (when cr60 = n, crh60 = m (m < n))......................................... 151 7-24 timing of carrier generator operation (when cr60 = crh60 = n)........................................................... 1 52 7-25 operation timing in pwm free-running mode (when rising edge is selected)....................................... 153 7-26 operation timing when overwriting cr50 (when rising edge is selected) ............................................. 154 7-27 operation timing in pwm free-running mode (when both edges are selected)..................................... 155 7-28 operation timing in pwm free-running mode (when both edges are selected) (when cr50 is overwritten)..................................................................................................... ................... 156 7-29 pwm pulse generator mode timing (basic operation) ........................................................................ ...... 158 7-30 pwm pulse generator mode timing (when cr6m and crh6m are overwritten)..................................... 159 7-31 start timing of 8-bit timer counter ...................................................................................... ....................... 160 7-32 timing of operation as external event counter (8-bit resolution) ......................................................... .... 160 8-1 block diagram of watch timer .............................................................................................. ...................... 161 8-2 format of watch timer mode control register ............................................................................... ............ 163 8-3 format of watch timer interrupt time selection register ................................................................... ....... 164 8-4 watch timer/interval timer operation timing............................................................................... .............. 166 9-1 block diagram of watchdog timer ........................................................................................... ................... 168 9-2 format of watchdog timer clock selection register......................................................................... ......... 169 9-3 format of watchdog timer mode register.................................................................................... .............. 170 10-1 block diagram of 8-bit a/d converter ..................................................................................... .................... 174 10-2 format of a/d converter mode register 0 .................................................................................. ................ 176 10-3 format of a/d converter mode register 1 .................................................................................. ................ 177 10-4 format of analog input channel specification register 0 .................................................................. ......... 178 10-5 basic operation of 8-bit a/d converter ................................................................................... .................... 180 10-6 relationship between analog input voltage and a/d conversion result ................................................... 181 10-7 software-started a/d conversion.......................................................................................... ...................... 182 10-8 how to reduce power consumption in standby mode.......................................................................... ..... 183 10-9 conversion result read timing (if conversion result is undefined) ........................................................ . 184 10-10 conversion result read timing (if conversion result is normal).......................................................... .... 184 10-11 analog input pin treatment .............................................................................................. ........................... 185 10-12 a/d conversion end interrupt request generation timing.................................................................. ....... 186 10-13 av dd pin handling .................................................................................................................. ..................... 186 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 19 list of figures (4/6) figure no. title page 11-1 block diagram of serial interface 20 ..................................................................................... .......................188 11-2 block diagram of baud rate generator 20 .................................................................................. ................189 11-3 format of serial operation mode register 20.............................................................................. ................191 11-4 format of asynchronous serial interface mode register 20................................................................. .......192 11-5 format of asynchronous serial interface status register 20............................................................... ........194 11-6 format of baud rate generator control register 20 ........................................................................ ...........195 11-7 format of asynchronous serial interface transmit/receive data............................................................ ....205 11-8 asynchronous serial interface transmission completion interrupt timing..................................................2 07 11-9 asynchronous serial interface reception completion interrupt timing ...................................................... .208 11-10 receive error timing.................................................................................................... ................................209 11-11 3-wire serial i/o mode timing ........................................................................................... ..........................215 12-1 block diagram of serial interface 1a0.................................................................................... ......................218 12-2 format of serial operation mode register 1a0 ............................................................................. ..............221 12-3 format of automatic data transmit/receive control register 0............................................................. .....222 12-4 format of automatic data transmit/receive interval specification register 0 ............................................22 3 12-5 3-wire serial i/o mode timing ............................................................................................ .........................228 12-6 circuit of switching in transfer bit order ............................................................................... ......................230 12-7 basic transmit/receive mode operation timings ............................................................................ ...........237 12-8 basic transmit/receive mode flowchart .................................................................................... .................238 12-9 buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode)....................239 12-10 basic transmit mode operation timings ................................................................................... ..................241 12-11 basic transmit mode flowchart ........................................................................................... ........................242 12-12 buffer ram operation in 6-byte transmission (in basic transmit mode).................................................... 243 12-13 repeat transmit mode operation timing ................................................................................... .................245 12-14 repeat transmit mode flowchart .......................................................................................... ......................246 12-15 buffer ram operation in 6-byte transmission (in repeat transmit mode) .................................................24 7 12-16 automatic transmission/reception suspension and restart................................................................. ......249 12-17 interval time of automatic transmission/reception ....................................................................... .............250 13-1 correspondence with lcd display ram...................................................................................... ................252 13-2 lcd controller/driver block diagram...................................................................................... .....................253 13-3 format of lcd display mode register 0.................................................................................... ..................254 13-4 format of lcd clock control register 0 ................................................................................... ...................255 13-5 relationship between lcd display data memory contents and segment/common outputs (when using s16 to s27)........................................................................................................ .....................256 13-6 common signal waveforms.................................................................................................. .......................258 13-7 voltages and phases of common and segment signals........................................................................ .....258 13-8 three-time slot lcd display pattern and electrode connections ............................................................ ..259 www.datasheet.co.kr datasheet pdf - http://www..net/
20 user?s manual u15400ej3v0ud list of figures (5/6) figure no. title page 13-9 example of connecting three-time slice lcd panel......................................................................... ........ 260 13-10 three-time slice lcd drive waveform examples (1/3 bias method) ........................................................ 26 1 13-11 four-time slice lcd display pattern and electrode connections........................................................... ... 262 13-12 example of connecting four-time slice lcd panel......................................................................... .......... 263 13-13 four-time slice lcd drive waveform examples (1/3 bias method) .......................................................... 2 64 13-14 example of lcd drive power connections ................................................................................... .............. 265 14-1 block diagram of multiplier .............................................................................................. ............................ 267 14-2 multiplier control register 0 format ..................................................................................... ....................... 268 14-3 multiplier operation timing (example of aah d3h) ................................................................................. 269 15-1 block diagram of remote controller receiver .............................................................................. .............. 271 15-2 operation examples of rmsr, rmscr, and rmdr registers when receiving 1010101011111111b (16 bits)..................................................................................... .... 272 15-3 format of remote controller receive control register ..................................................................... ......... 276 15-4 example of type a data format ............................................................................................ ..................... 278 15-5 operation flow of type a reception mode.................................................................................. ............... 279 15-6 setting example (where n1 = 1, n2 = 2)...................................................................................................... 283 15-7 generation timing of intrerr signal ...................................................................................... ................. 285 15-8 noise elimination operation example ...................................................................................... ................... 287 16-1 basic configuration of interrupt function ................................................................................ .................... 291 16-2 format of interrupt request flag registers ............................................................................... ................. 293 16-3 format of interrupt mask flag registers .................................................................................. ................... 294 16-4 format of external interrupt mode registers.............................................................................. ................. 295 16-5 program status word configuration........................................................................................ .................... 296 16-6 format of key return mode register 00 .................................................................................... ................. 297 16-7 block diagram of falling edge detector................................................................................... ................... 297 16-8 format of key return mode register 01 .................................................................................... ................. 298 16-9 block diagram of falling edge detector................................................................................... ................... 298 16-10 flow from generation of non-maskable interrupt request to acknowledgment ......................................... 300 16-11 timing of non-maskable interrupt request acknowledgment................................................................. .... 300 16-12 non-maskable interrupt request acknowledgment ........................................................................... ......... 300 16-13 interrupt request acknowledgment program algorithm...................................................................... ........ 301 16-14 interrupt request acknowledgment timing (example: mov a, r)............................................................. .. 302 16-15 interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execution) ............................................ 302 16-16 example of multiple interrupts .......................................................................................... ........................... 303 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 21 list of figures (6/6) figure no. title page 17-1 format of oscillation stabilization time selection register .............................................................. ...........306 17-2 releasing halt mode by interrupt ......................................................................................... .....................308 17-3 releasing halt mode by reset input....................................................................................... ................309 17-4 releasing stop mode by interrupt......................................................................................... .....................311 17-5 releasing stop mode by reset input ....................................................................................... ...............312 18-1 block diagram of reset function .......................................................................................... .......................313 18-2 reset timing by reset input.............................................................................................. ........................314 18-3 reset timing by overflow in watchdog timer ............................................................................... ..............314 18-4 reset timing by reset input in stop mode ................................................................................. ............314 19-1 environment for writing program to flash memory.......................................................................... ............318 19-2 communication mode selection format ...................................................................................... ................319 19-3 example of connection with dedicated flash programmer .................................................................... .....320 19-4 v pp pin connection example........................................................................................................ ................322 19-5 signal conflict (input pin of serial interface).......................................................................... ......................323 19-6 abnormal operation of other device ....................................................................................... ....................323 19-7 signal conflict (reset pin) .............................................................................................. ...........................324 19-8 wiring example for flash writing adapter with 3-wire serial i/o.......................................................... .......325 19-9 wiring example for flash writing adapter with 3-wire serial i/o with handshake ......................................326 19-10 wiring example for flash writing adapter with uart ...................................................................... ...........327 a-1 development tools......................................................................................................... ..............................378 b-1 distance between in-circuit emulator and conversion socket (80gc) .......................................................38 3 b-2 connection conditions of target system (when np-80gc-tq is used) ....................................................384 b-3 connection conditions of target system (when np-h80gc-tq is used)..................................................384 b-4 distance between in-circuit emulator and conversion adapter (80gk)......................................................38 5 b-5 connection conditions of target system (when np-80gk is used)...........................................................38 6 b-6 connection conditions of target system (when np-h80gk-tq is used) ..................................................386 www.datasheet.co.kr datasheet pdf - http://www..net/
22 user?s manual u15400ej3v0ud list of tables (1/2) table no. title page 2-1 types of pin i/o circuits................................................................................................. ............................... 42 3-1 internal rom capacity ..................................................................................................... ............................. 51 3-2 vector table .............................................................................................................. .................................... 51 3-3 internal high-speed ram and internal low-speed ram........................................................................ ...... 52 3-4 special function registers................................................................................................ ............................ 63 4-1 port functions ............................................................................................................ ................................... 76 4-2 configuration of port..................................................................................................... ................................. 76 4-3 port mode registers and output latch settings when using alternate functions....................................... 92 5-1 configuration of clock generator .......................................................................................... ........................ 95 5-2 maximum time required for switching cpu clock............................................................................. ........ 106 6-1 16-bit timer 20 configuration............................................................................................. ......................... 108 6-2 interval time of 16-bit timer 20 .......................................................................................... ........................ 113 6-3 settings of capture edge .................................................................................................. .......................... 116 7-1 operation modes ........................................................................................................... .............................. 120 7-2 configuration of 8-bit timers 50, 60, and 61 .............................................................................. ................. 122 7-3 interval time of timer 50................................................................................................. ............................ 135 7-4 interval time of timer 60................................................................................................. ............................ 135 7-5 interval time of timer 61................................................................................................. ............................ 135 7-6 square-wave output range of timer 50 ...................................................................................... .............. 141 7-7 square-wave output range of timer 60 ...................................................................................... .............. 142 7-8 square-wave output range of timer 61 ...................................................................................... .............. 142 7-9 interval time with 16-bit resolution ...................................................................................... ...................... 143 7-10 square-wave output range with 16-bit resolution.......................................................................... .......... 147 8-1 interval time of interval timer ........................................................................................... .......................... 162 8-2 configuration of watch timer .............................................................................................. ........................ 162 8-3 interval time of interval timer ........................................................................................... .......................... 165 9-1 watchdog timer program loop detection time ................................................................................ ......... 167 9-2 interval time............................................................................................................. ................................... 167 9-3 configuration of watchdog timer ........................................................................................... ..................... 168 9-4 watchdog timer program loop detection time ................................................................................ ......... 171 9-5 interval time of interval timer ........................................................................................... .......................... 172 10-1 configuration of 8-bit a/d converter ..................................................................................... ...................... 173 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 23 list of tables (2/2) table no. title page 11-1 configuration of serial interface 20 ..................................................................................... .........................187 11-2 serial interface 20 operation mode settings.............................................................................. ..................193 11-3 example of relationships between system clock and baud rate .............................................................. 196 11-4 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) .......197 11-5 example of relationships between system clock and baud rate .............................................................. 204 11-6 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) .......204 11-7 receive error causes ..................................................................................................... .............................209 12-1 configuration of serial interface 1a0.................................................................................... ........................217 12-2 timing of interrupt request signal generation ............................................................................ ................250 13-1 maximum number of display pixels......................................................................................... ....................251 13-2 configuration of lcd controller/driver................................................................................... ......................251 13-3 frame frequencies (hz)................................................................................................... ............................255 13-4 com signals .............................................................................................................. ..................................257 13-5 select and deselect voltages (com0 to com2).............................................................................. ............259 13-6 select and deselect voltages (com0 to com3).............................................................................. ............262 15-1 remote controller receiver configuration................................................................................. ..................270 15-2 noise elimination width.................................................................................................. ..............................286 16-1 interrupt source......................................................................................................... ...................................290 16-2 flags corresponding to interrupt request signal name..................................................................... .........292 16-3 time from generation of maskable interrupt request to servicing.......................................................... ....301 17-1 operation statuses in halt mode.......................................................................................... .....................307 17-2 operation after releasing halt mode ...................................................................................... ..................309 17-3 operation statuses in stop mode .......................................................................................... ....................310 17-4 operation after releasing stop mode ...................................................................................... .................312 18-1 status of hardware after reset........................................................................................... .........................315 19-1 differences between pd78f9478, 78f9479, and mask rom version ......................................................317 19-2 communication mode list .................................................................................................. ..........................319 19-3 pin connection list ...................................................................................................... ................................321 21-1 operand identifiers and description methods .............................................................................. ................330 25-1 surface mounting type soldering conditions ............................................................................... ...............376 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 24 chapter 1 general 1.1 features rom and ram capacities data memory item part number program memory (rom) internal ram lcd display ram pD789477 24 kb 768 bytes pd789478 32 kb 1,024 bytes 28 4 bits pd789479 note mask rom 48 kb 1,536 bytes pd78f9478 32 kb 1,024 bytes pd78f9479 note flash memory 48 kb 1,536 bytes minimum instruction execution time can be selected from high speed (0.4 s: @5.0 mhz operation with main system clock), low speed (1.6 s: @5.0 mhz operation with main system clock), and ultra low speed (122 s: @32.768 khz operation with subsystem clock) a circuit to multiply the subsystem clock by 4 is selectable (15.26 s: @131 khz operation: 32.768 khz subsystem clock 4) i/o ports: 45 (n-ch open-drain: 4) timer: 6 channels serial interface: 2 channels 8-bit resolution a/d converter: 8 channels lcd controller/driver (external resistance division method) segment signals: 28, common signals: 4 ? on-chip multiplier: 8 bits 8 bits = 16 bits on-chip infrared remote control reception function ? on-chip key return signal detector supply voltage: v dd = 1.8 to 5.5 v note under development 1.2 applications cd radio-cassette players, portable audio, compact cameras, healthcare equipment, etc. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general user?s manual u15400ej3v0ud 25 1.3 ordering information part number package internal rom pD789477gc- -8bt 80-pin plastic qfp (14 14) mask rom pd789478gc- -8bt 80-pin plastic qfp (14 14) mask rom pd789479gc- -8bt note 80-pin plastic qfp (14 14) mask rom pd789479gk- -9eu note 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd78f9478gc-8bt 80-pin plastic qfp (14 14) flash memory pd78f9479gc-8bt note 80-pin plastic qfp (14 14) flash memory pd78f9479gk-9eu note 80-pin plastic tqfp (fine pitch) (12 12) flash memory note under development remark indicates rom code suffix. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general 26 user?s manual u15400ej3v0ud 1.4 pin configuration (top view) (1) pD789477, 789478, 78f9478 80-pin plastic qfp (14 14) pD789477gc- -8bt pd789478gc- -8bt pd78f9478gc-8bt notes 1. whether to use pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) port function registers and chapter 20 mask options ). 2. whether to use these pins as i/o port pins (p80 to p87) or segment outputs (s20 to s27) can be selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) port function registers and chapter 20 mask options ). cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . remark the parenthesized values apply only to the pd78f9478. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc nc v lc2 v lc1 v lc0 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 p10 p11 p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/sck10 p24/so10 p25/si10 p30/intp0/to50/tmi60 p31/intp1/to60 p32/intp2/tmi61/to61 p33/intp3/cpt20/to20 p34/rin av ss p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 s11 s12 s13 s14 s15 p70/s16 note 1 p71/s17 note 1 p72/s18 note 1 p73/s19 note 1 p80/s20 note 2 p81/s21 note 2 p82/s22 note 2 p83/s23 note 2 p84/s24 note 2 p85/s25 note 2 p86/s26 note 2 p87/s27 note 2 av dd p67/ani7 p66/ani6 p50 p51 p52 p53 reset x2 x1 v ss v dd xt2 xt1 ic0 (v pp ) p00/kr0 p01/kr1 p02/kr2 p03/kr3 p04/kr4 p05/kr5 p06/kr6 p07/kr7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general user ? s manual u15400ej3v0ud 27 (2) pd789479, 78f9479 80-pin plastic qfp (14 14) pd789479gc- -8bt note 1 pd78f9479gc-8bt note 1 80-pin plastic tqfp (fine pitch) (12 12) pd789479gk- -9eu note 1 pd78f9479gk-9eu note 1 notes 1. under development 2. whether to use pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) port function registers and chapter 20 mask options ). 3. whether to use these pins as i/o port pins (p80 to p87) or segment outputs (s20 to s27) can be selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) port function registers and chapter 20 mask options ). cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . remark the parenthesized values apply only to the pd78f9479. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc nc v lc2 v lc1 v lc0 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 p10 p11 p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/sck10 p24/so10 p25/si10 p30/intp0/to50/tmi60 p31/intp1/to60 p32/intp2/tmi61/to61 p33/intp3/cpt20/to20 p34/rin av ss p60/ani0/kr10 p61/ani1/kr11 p62/ani2/kr12 p63/ani3/kr13 p64/ani4/kr14 p65/ani5/kr15 s11 s12 s13 s14 s15 p70/s16 p71/s17 p72/s18 p73/s19 p80/s20 p81/s21 p82/s22 p83/s23 p84/s24 p85/s25 p86/s26 p87/s27 av dd p67/ani7/kr17 p66/ani6/kr16 p50 p51 p52 p53 reset x2 x1 v ss v dd xt2 xt1 ic0 (v pp ) p00/kr00 p01/kr01 p02/kr02 p03/kr03 p04/kr04 p05/kr05 p06/kr06 p07/kr07 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 note 2 note 2 note 2 note 2 note 3 note 3 note 3 note 3 note 3 note 3 note 3 note 3 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general 28 user ? s manual u15400ej3v0ud pin name ani0 to ani7: analog input asck20: asynchronous serial input av : analog power supply av : analog ground com0 to com3: common output cpt20: capture trigger input ic0: internally connected intp0 to intp3: external interrupt input kr0 to kr7: key return kr00 to kr07: key return kr10 to kr17: key return nc: no-connect p00 to p07: port 0 p10, p11: port 1 p20 to p25: port 2 p30 to p34: port 3 p60 to p67: port 6 p70 to p73: port 7 p80 to p87: port 8 reset: reset rin: remote control input rxd0: receive data s0 to s27: segment output sck10: serial clock input/output si10: serial data input so10: serial data output sck20: serial block input/output si20: serial data input so20: serial data output tmi60, 61: timer input to20, 50, 60, 61: timer output txd0: transmit data v : power supply v to v : power supply for lcd v : programming power supply v : ground x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general user ? s manual u15400ej3v0ud 29 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same. 52-pin sio + resistance division method lcd (24 4) 8-bit a/d + internal voltage boosting method lcd (23 4) pd789327 lcd drive 80-pin 80-pin pd789436 pd789446 pd789426 pd789456 pd789417a pd789407a pd789316 pd789467 pd789306 pd789426 with 10-bit a/d pd789860 with enhanced timer function, sio, and expanded rom and ram pd789446 with 10-bit a/d sio + 8-bit a/d + resistance division method lcd (28 4) sio + 8-bit a/d + internal voltage boosting method lcd (15 4) pd789407a with 10-bit a/d sio + 8-bit a/d + internal voltage boosting method lcd (5 4) rc oscillation version of pd789306 sio + internal voltage boosting method lcd (24 4) 64-pin 64-pin 52-pin 64-pin 64-pin 64-pin sio + 10-bit a/d + internal voltage boosting method lcd (28 4) 80-pin sio + 8-bit a/d + resistance division method lcd (28 4) 80-pin pd789478 pd789488 64-pin products under development products in mass production small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer function and expanded rom and ram on-chip uart and capable of low-voltage (1.8 v) operation pd789074 with subsystem clock added inverter control 44-pin pd789842 on-chip inverter controller and uart pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d function 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with 10-bit a/d pd789104a with enhanced timer pd789124a with 10-bit a/d rc oscillation version of pd789104a pd789104a with 10-bit a/d pd789026 with 8-bit a/d and multiplier added pd789104a with eeprom added pd789146 with 10-bit a/d pd789177y pd789167y y subseries supports smb. usb 88-pin pd789830 pd789835 144-pin uart + dot lcd (40 16) uart + 8-bit a/d + dot lcd (total display outputs: 96) 42-/44-pin 44-pin 30-pin 20-pin 20-pin pd789026 with enhanced timer function rc oscillation version of pd789052 vfd drive 52-pin 64-pin pd789871 on-chip vfd controller (total display outputs: 25) meter control pd789881 uart + resistance division method lcd (26 4) 30-pin pd789074 with enhanced timer function and expanded rom and ram 44-pin pd789800 for pc keyboard. on-chip usb function keyless entry 20-pin 20-pin 30-pin on-chip poc and key return circuit rc oscillation version of pd789860 on-chip bus controller 30-pin pd789850 on-chip dcan controller pd789074 pd789088 pd789062 pd789014 pd789046 pd789026 pd789053 pd789860 pd789861 pd789862 pd789860 without eeprom tm , poc, and lvi www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general 30 user ? s manual u15400ej3v0ud the major differences between the subseries are shown below. series for general-purpose applications and lcd drive timer v function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks pd789046 16 k 1 ch pd789026 4 k to 16 k 1 ch 34 pd789088 16 k to 32 k 3 ch pd789074 2 k to 8 k 1 ch 1 ch 24 pd789014 2 k to 4 k 1 ch (uart: 1ch) 22 ? pd789062 rc-oscillation version small- scale package, general- purpose applica- tions pd789052 4 k 2 ch ? ? 1 ch ?? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 k to 24 k 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 k to 16 k 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc-oscillation version pd789114a ? 4 ch small- scale package, general- purpose applica- tions + a/d converter pd789104a 2 k to 8 k 1 ch 1 ch ? 1ch 4 ch ? 1 ch (uart: 1ch) 20 1.8 v ? pd789835 24 k to 60 k 6 ch ? 3 ch 37 1.8 v note pd789830 24 k 1 ch ? 1 ch (uart: 1ch) 30 2.7 v dot lcd supported pd789488 32 k to 48 k ? 8 ch pd789478 24 k to 48 k 8 ch ? 2 ch (uart: 1ch) 45 pd789417a ? 7 ch pd789407a 12 k to 24 k 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 k to 16 k 6 ch 1 ch (uart: 1ch) 40 ? pd789316 rc-oscillation version pd789306 8 k to 16 k 1 ch ? 2 ch (uart: 1ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 k to 24 k 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? note flash memory version: 3.0 v www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general user ? s manual u15400ej3v0ud 31 series for assp timer v function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks usb pd789800 8 k 2 ch ?? 1 ch ?? 2 ch (usb: 1ch) 31 4.0 v ? inverter control pd789842 8 k to 16 k 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1ch) 30 4.0 v ? on-chip bus controller pd789850 16 k 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1ch) 18 4.0 v ? pd789861 rc-oscillation version, on-chip eeprom pd789860 4 k 2 ch ?? 1 ch ?? ? 14 keyless entry pd789862 16 k 1 ch 2 ch 1 ch (uart: 1ch) 22 1.8 v on-chip eeprom vfd drive pd789871 4 k to 8 k 3 ch ? 1 ch 1 ch ?? 1 ch 33 2.7 v ? meter control pd789881 16 k 2 ch 1 ch ? 1 ch ?? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general 32 user?s manual u15400ej3v0ud 1.6 block diagram notes 1. whether to use these pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option in the pD789477, 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 2. whether to use these pins as i/o port pins (p80 to p87) or segment outputs (s20 to s27) can be selected in 1-bit units by means of a mask option in the pD789477, 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 3. pD789477, 789478, and 78f9478 only. 4. pd789479 and 78f9479 only. remark the parenthesized values apply only to the pd78f9478 and 78f9479. 78k/0s cpu core rom (flash memory) ram v dd v ss ic0 (v pp ) cpt20/to20/p33 8-bit timer/ event counter 60 p00 to p07 port 0 p10 to p11 port 1 p20 to p25 port 2 p30 to p34 port 3 p50 to p53 port 5 p60 to p67 port 6 p70 to p73 note 1 port 7 8-bit timer/ event counter 61 16-bit timer 20 watch timer watchdog timer serial interface 20 to50/p30 to60/p31 sck20/asck20/p20 si20/rxd20/p22 so20/txd20/p21 a/d converter ani0/p60 to ani7/p67 av dd av ss v lc0 to v lc2 s0 to s15 com0 to com3 lcd controller/ driver system control reset x1 x2 xt1 xt2 interrupt control p80 to p87 note 2 port 8 standby control intp0/p30 to intp3/p33 ram space for lcd data 8-bit timer 50 tmi60/p30 tmi61/to61/p32 remote control signal receiver rin/p34 serial interface 1a0 sck10/p23 si10/p25 so10/p24 s16 to s19 note 1 s20 to s27 note 2 multiplier key return kr0/p00 to kr7/p07 note 3 kr00/p00 to kr07/p07 note 4 kr10/p60/ani0 to kr17/p67/ani7 note 4 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general user ? s manual u15400ej3v0ud 33 1.7 overview of functions (1/2) item pD789477 pd789478 pd78f9478 pd789479 note 1 pd78f9479 note 1 rom 24 kb 32 kb 32 kb (flash memory) 48 kb 48 kb (flash memory) high-speed ram 768 bytes 1024 bytes 1536 bytes low-speed ram ? 512 bytes internal memory lcd display ram 28 bytes main system clock (oscillation frequency) ceramic/crystal oscillation (1.0 to 5.0 mhz) subsystem clock (oscillation frequency) crystal oscillation (32.768 khz) 0.4 s/1.6 s (@5.0 mhz operation with main system clock) 122 s (@32.768 khz operation with sub system clock) minimum instruction execution time 15.26 s (@131 khz operation with 4 subsystem clock) subsystem clock multiplication function 4 multiplication circuit (operating supply voltage: v dd = 2.7 to 5.5 v) note 2 general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulation (set, reset, test) etc. multiplier 8 bits 8 bits = 16 bits i/o ports total: 45 note 3 cmos i/o: 29 cmos input: 12 n-ch open-drain i/o: 4 timers ? 16-bit timer: 1 channel ? 8-bit timer: 3 channels ? watch timer: 1 channel ? watchdog timer: 1 channel timer outputs 4 serial interface uart/3-wire serial i/o mode: 1 channel 3-wire serial i/o mode (with automatic transfer function): 1 channel a/d converter 8-bit resolution 8 channels lcd controller/driver ? segment signal outputs: 28 note 3 ? common signal outputs: 4 power supply method for lcd drive external resistance division method infrared remote control reception function on-chip key return signal detection function 8 pins 16 pins maskable internal: 16, external: 5 internal: 16, external: 6 vectored interrupt sources non-maskable internal: 1 notes 1. under development 2. whether a circuit to multiply the clock by 4 is used or not is selected by a mask option or the subclock selection register. 3. 12 pins are used either as a port function or lcd segment output selected by a mask option or port function register. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 1 general 34 user ? s manual u15400ej3v0ud (2/2) item pD789477 pd789478 pd78f9478 pd789479 note pd78f9479 note reset ? reset by reset signal input ? internal reset by watchdog timer supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package ? 80-pin plastic qfp (14 14) ? 80-pin plastic qfp (14 14) ? 80-pin plastic tqfp (fine pitch) (12 12) note under development an outline of the timer is shown below. 16-bit timer 20 8-bit timer 50 8-bit timer 60 8-bit timer 61 watch timer watchdog timer interval timer ? ? ? ? 1 channel 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter ? ? ? ?? ? ? ? 1 channel 1 channel ? ? ? ?? ? ? ? timer outputs 1 output 1 output 1 output 1 output ? ? ? ?? ? ? ? square-wave outputs ? ? ? ? 1 output 1 output 1 output ? ? ? ?? ? ? ? capture 1 input ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? function interrupt sources 1 1 1 1 2 2 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or interval timer function. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 35 chapter 2 pin functions 2.1 list of pin functions (1) port pins (1/2) pin name i/o function after reset alternate function p00 to p07 i/o port 0. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b0 (pub0) or the key return mode register (krm00). input kr0 to kr7 note 1 kr00 to kr07 note 2 p10, p11 i/o port 1. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b1 (pub1). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 sck10 p24 so10 p25 i/o port 2. 6-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b2 (pub2). input si10 p30 intp0/to50/tmi60 p31 intp1/to60 p32 intp2/tmi61/to61 p33 intp3/cpt20/to20 p34 i/o port 3. 5-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified in 1-bit units by means of pull-up resistor option register b3 (pub3). input rin p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for mask rom version, an on-chip pull-up resistor can be specified by means of mask option. input ? p60 to p67 input port 6. 8-bit input port. input ani0 to ani7 note 1 ani0/kr10- ani7/kr17 note 2 notes 1. pD789477, 789478, and 78f9478 only 2. pd789479 and 78f9479 only www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user?s manual u15400ej3v0ud 36 (1) port pins (2/2) pin name i/o function after reset alternate function p70 to p73 note 1 input port 7. 4-bit input port. (only when input port is selected by mask option or port function register) input ? p80 to p87 note 2 i/o port 8. 8-bit i/o port. (only when i/o port is selected by mask option or port function register) input ? notes 1. whether to use these pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option in the pD789477, 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 2. whether to use these pins as i/o port pins (p80 to p87) or segment outputs (s20 to s27) can be selected in 1-bit units by means of a mask option in the pD789477 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 p30/to50/tmi60 intp1 p31/to60 intp2 p32/tmi61/to61 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. input p33/cpt20/to20 kr0 to kr7 note 1 input key return signal detection input p00 to p07 kr00 to kr07 note 2 p00 to p07 kr10 to kr17 note 2 input key return signal detection input p60/ani0 to p67/ani7 to20 output 16-bit timer 20 output input p33/intp3/cpt20 cpt20 output capture edge input of 16-bit timer 20 input p33/intp3/to20 to50 output 8-bit timer 50 output input p30/intp0/tmi60 to60 output 8-bit timer 60 output input p31/intp1 to61 output 8-bit timer 61 output input p32/intp2/tmi61 tmi60 input external count clock input to 8-bit timer 60 input p30/intp0/to50 tmi61 input external count clock input to 8-bit timer 61 input p32/intp2/to61 sck20 p20/asck20 sck10 i/o serial clock input/output of serial interface input p23 so20 p21/txd20 so10 output serial data output of serial interface input p24 si20 p22/rxd20 si10 input serial data input of serial interface input p25 asck20 input serial clock input of asynchronous serial interface input p20/sck20 notes 1. pD789477, 789478, and 78f9478 only 2. pd789479 and 78f9479 only www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user?s manual u15400ej3v0ud 37 (2) non-port pins (2/2) pin name i/o function after reset alternate function txd20 output serial data output of asynchronous serial interface input p21/so20 rxd20 input serial data input of asynchronous serial interface input p22/si20 rin input remote control receive data input input p34 s0 to s15 lcd controller/driver segment signal outputs ? s16 to s19 note 1 only when segment output is selected by mask option ? s20 to s27 note 2 output only when segment output is selected by mask option low-level output ? com0 to com3 output lcd controller/driver common signal outputs low-level output ? v lc0 to v lc2 ? lcd drive voltage ? ? ani0 to ani7 ? a/d converter analog input ? p60 to p67 note 3 p60/kr10 to p67/kr17 note 4 av ss ? a/d converter ground potential ? ? av dd ? a/d converter analog power supply ? ? x1 input ? ? x2 ? connecting crystal resonator for main system clock oscillation ?? xt1 input ?? xt2 ? connecting crystal resonator for sub system clock oscillation ?? reset input system reset input input ? v dd ? positive power supply ? ? v ss ? ground potential ? ? ic0 ? internally connected. connect directly to v ss .?? nc ? not internally connected. leave open. ? ? v pp ? sets flash memory programming mode. used to apply high voltage when a program is written or verified. ?? notes 1. whether to use these pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option in the pD789477, 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 2. whether to use these pins as i/o port pins (p80 to p87) or segment outputs (s20 to s27) can be selected in 1-bit units by means of a mask option in the pD789477 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 2. pD789477, 789478, and 78f9478 only 3. pd789479 and 78f9479 only www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user?s manual u15400ej3v0ud 38 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) these pins constitute an 8-bit i/o port. in addition, these pins enable key return signal detection. port 0 can be specified in the following operation modes in 1-bit units. (1) port mode these pins constitute an 8-bit i/o port and can be set in the input or output port mode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b0 (pub0) in 1-bit units. (2) control mode in this mode, p00 to p07 function as key return signal detection pins (kr0 to kr7 ( pD789477, 789478, 78f9478), kr00 to kr07 ( pd789479, 78f9479)). 2.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set in the input or output port mode in 1-bit units by port mode register 1 (pm1). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b1 (pub1) in 1-bit units. 2.2.3 p20 to p25 (port 2) these pins constitute a 6-bit i/o port. in addition, these pins enable serial interface data i/o and serial clock i/o. port 2 can be specified in the following operation modes in 1-bit units. (1) port mode in this mode, p20 to p25 function as a 6-bit i/o port. port 2 can be set in the input or output port mode in 1- bit units by port mode register 2 (pm2). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b2 (pub2) in 1-bit units. (2) control mode in this mode, p20 to p25 function as the serial interface data i/o and serial clock i/o. (a) si20, so20, si10, so10 these are the serial data i/o pins of the serial interface. (b) sck20, sck10 these are the serial clock i/o pins of the serial interface. (c) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface. (d) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using p20 to p25 as serial interface pins, the i/o mode and output latch must be set according to the functions to be used. for the details of the setting, refer to table 11-2 serial interface 20 operation mode setting and 12.3 (1) serial operation mode register 1a0 (csim1a0). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user?s manual u15400ej3v0ud 39 2.2.4 p30 to p34 (port 3) these pins constitute a 5-bit i/o port. in addition, they also function as timer i/o, external interrupt inputs, and input of remote control receive data. port 3 can be specified in the following operation modes in 1-bit units. (1) port mode in this mode, p30 to p34 function as a 5-bit i/o port. port 3 can be set in the input or output port mode in 1- bit units by port mode register 3 (pm3). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register b3 (pub3) in 1-bit units. (2) control mode in this mode, p30 to p34 function as timer i/o, external interrupt inputs, and input of remote control receive data. (a) tmi60, tmi61 these are the external clock input pins of timers 60 and 61. (b) to20, to50, to60, to61 these are the timer output pins of timers 20, 50, 60, and 61. (c) cpt20 this is the capture edge input pin of 16-bit timer 20. (d) intp0 to intp3 these are external interrupt input pins for which valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. (e) rin this is the data input pin of the remote control receiver. 2.2.5 p50 to p53 (port 5) these pins constitute a 4-bit n-ch open-drain i/o port. port 5 can be set in the input or output port mode in 1-bit units by port mode register 5 (pm5). in the mask rom version, use of an on-chip pull-up resistor can be specified by a mask option in 1-bit units. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user?s manual u15400ej3v0ud 40 2.2.6 p60 to p67 (port 6) this is an 8-bit input-only port. in addition to a general-purpose input port function, it has an a/d converter input function and key return signal detection function note . (1) port mode in this mode, p60 to p67 function as an 8-bit input-only port. (2) control mode in this mode, p60 to p67 function as the analog inputs of the a/d converter and key return signal detection pins note . (a) ani0 to ani7 these are the analog input pins of the a/d converter. (b) kr10 to kr17 note these are the key return signal detection pins. note pd789479 and 78f9479 only 2.2.7 p70 to p73 (port 7) these pins constitute a 4-bit input-only port. this port can be used only when the port function is selected by a mask option in the pD789477, 789478, and 789479 or by a port function register in the pd78f9478 and 78f9479. 2.2.8 p80 to p87 (port 8) these pins constitute an 8-bit i/o port. port 8 can be set in the input or output mode in 1-bit units by port mode register 8 (pm8). this port can be used only when the port function is selected by a mask option in the pD789477, 789478 and 789479 or by a port function register in the pd78f9478 and 78f9479. 2.2.9 s0 to s27 note these pins are the segment signal output pins for the lcd controller/driver. note pins s16 through s27 can be used only when segment output is selected by a mask option in the pD789477, 789478, and 789479 or by a port function register in the pd78f9478 and 78f9479. 2.2.10 com0 to com3 these pins are the common signal output pins for the lcd controller/driver. 2.2.11 v lc0 to v lc2 these pins are power supply voltage pins for driving the lcd. 2.2.12 nc the nc (no-connect) pin is not internally connected. connect this pin to v ss . (it can also be left open.) 2.2.13 reset this pin inputs an active-low system reset signal. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user?s manual u15400ej3v0ud 41 2.2.14 x1, x2 these pins are used to connect a crystal resonator for main system clock oscillation. to supply an external clock, input the clock to x1 and input the inverted signal to x2. 2.2.15 xt1, xt2 these pins are used to connect a crystal resonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 2.2.16 a vdd this is the analog power supply pin of the a/d converter. always use the same potential as that of the v dd pin even when the a/d converter is not used. 2.2.17 av ss this is the ground potential pin of the a/d converter. always use the same potential as that of the v ss pin even when the a/d converter is not used. 2.2.18 v dd this is the positive power supply pin. 2.2.19 v ss this is the ground pin. 2.2.20 v pp (flash memory version only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. handle the pins in either of the following ways. ? independently connect a 10 k ? pull-down resistor. ? switch this pin to be directly connected to the dedicated flash programmer in programming mode or to v ss in normal operation mode using a jumper on the board. if there is a potential difference between the v pp pin and v ss pin due to a long wiring length or external noise superimposed on the v pp pin, the user program may not run correctly. 2.2.21 ic0 (mask rom version only) the ic0 (internally connected) pin is used to set the pd789478 subseries in the test mode before shipment. in the normal operation mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if there is a potential difference between the ic0 pin and v ss pin due to a long wiring length or external noise superimposed on the ic0 pin, the user program may not run correctly. ? directly connect the ic0 pin to the v ss pin. v ss ic0 keep short www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user ? s manual u15400ej3v0ud 42 2.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the i/o circuit configuration of each type, see figure 2-1. table 2-1. types of pin i/o circuits (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/kr0 to p07/kr7 note 1 p00/kr00 to p07/kr07 note 2 8-a p10, p11 5-a p20/sck20/asck20 8-a p21/so20/txd20 5-a p22/si20/rxd20 p23/sck10 8-a p24/so10 5-a p25/si10 input: independently connect to v dd or v ss via a resistor. output: leave open. p30/intp0/to50/tmi60 p31/intp1/to60 p32/intp2/to61/tmi61 p33/intp3/cpt20/to20 p34/rin 8-a input: independently connect to v ss via a resistor. output: leave open. p50 to p53 (mask rom version) 13-w p50 to p53 (flash memory version) 13-v i/o input: independently connect to v dd via a resistor. output: leave open. p60/ani0 to p67/ani7 note 1 p60/ani10/kr10 to p67/ani17/kr17 note 2 9-c p70 to p73 note 3 2-h input connect directly to v dd or v ss . p80 to p87 note 3 5-k i/o input: independently connect to v dd or v ss via a resistor. output: leave open. com0 to com3 18 s0 to s15 s16 to s19 note 4 s20 to s27 note 4 17 output nc v lc0 to v lc2 leave open. av dd connect directly to v dd . av ss ?? connect directly to v ss . notes 1. pD789477, 789478, and 78f9478 only 2. pd789479 and 78f9479 only 3. only when port pin is selected by mask option or port function register. 4. only when segment output pin is selected by mask option or port function register. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user ? s manual u15400ej3v0ud 43 table 2-1. types of pin i/o circuits (2/2) pin name i/o circuit type i/o recommended connection of unused pins xt1 input connect directly to v ss . xt2 ? ? leave open. reset 2 input ? ic0 connect directly to v ss . v pp ?? independently connect a 10 k ? pull-down resistor, or connect directly to v ss . www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user ? s manual u15400ej3v0ud 44 figure 2-1. i/o circuit types (1/2) type 2 type 2-h schmitt-triggered input with hysteresis characteristics. in input enable in type 5-a type 5-k pull-up enable v dd p-ch p-ch in/out data output disable input enable v dd n-ch v ss data output disable input enable v dd p-ch in/out n -ch type 8-a type 9-c pull-up enable v dd p-ch data v dd p-ch output disable in/out n-ch v ss in comparator v ref (threshold voltage) av ss p-ch n-ch input enable + www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 2 pin functions user ? s manual u15400ej3v0ud 45 figure 2-1. i/o circuit types (2/2) type 13-w type 13-v data output disable input enable in/out n -ch v ss mask option v dd middle-voltage input buffer data output disable input enable in/out n -ch v ss middle-voltage input buffer type 17 type 18 p-ch n-ch p-ch n-ch n-ch n-ch data out v lc0 v lc1 seg v lc2 p-ch p-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch data p-ch n-ch v lc1 v lc0 v lc2 out com www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 46 chapter 3 cpu architecture 3.1 memory space the pd789478 subseries can access 64 kb of memory space. figures 3-1 to 3-5 show the memory maps. figure 3-1. memory map ( pD789477) 6 0 0 0 h 5 f f f h special function registers 256 8 bits internal high-speed ram 768 8 bits lcd display ram 28 4 bits f f f f h f f 0 0 h f e f f h f c 0 0 h f b f f h 0 0 0 0 h program memory space data memory space 5 f f f h 0 0 0 0 h program area 0 0 8 0 h 0 0 7 f h program area 0 0 4 0 h 0 0 3 f h callt table area reserved 0 0 2 e h 0 0 2 d h vector table area internal rom 24,576 8 bits f a 1 c h f a 1 b h f a 0 0 h f 9 f f h reserved www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 47 figure 3-2. memory map ( pd789478) 8 0 0 0 h 7 f f f h special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits f f f f h f f 0 0 h f e f f h f b 0 0 h f a f f h 0 0 0 0 h program memory space data memory space 7 f f f h 0 0 0 0 h program area 0 0 8 0 h 0 0 7 f h program area 0 0 4 0 h 0 0 3 f h callt table area reserved 0 0 2 e h 0 0 2 d h vector table area internal rom 32,768 8 bits f a 1 c h f a 1 b h f a 0 0 h f 9 f f h reserved www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 48 figure 3-3. memory map ( pd78f9478) 8 0 0 0 h 7 f f f h special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits f f f f h f f 0 0 h f e f f h f b 0 0 h f a f f h 0 0 0 0 h program memory space data memory space 7 f f f h 0 0 0 0 h program area 0 0 8 0 h 0 0 7 f h program area 0 0 4 0 h 0 0 3 f h callt table area reserved 0 0 2 e h 0 0 2 d h vector table area flash memory 32,768 8 bits f a 1 c h f a 1 b h f a 0 0 h f 9 f f h reserved www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 49 figure 3-4. memory map ( pd789479) f 7 0 0 h f 6 f f h special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits f f f f h f f 0 0 h f e f f h f b 0 0 h f a f f h 0 0 0 0 h program memory space data memory space b f f f h 0 0 0 0 h program area 0 0 8 0 h 0 0 7 f h program area 0 0 4 0 h 0 0 3 f h callt table area reserved 0 0 3 0 h 0 0 2 f h vector table area internal rom 49,152 8 bits f a 1 c h f a 1 b h f a 0 0 h f 9 f f h reserved reserved internal low-speed ram 512 8 bits f 5 0 0 h f 4 f f h c 0 0 0 h b f f f h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 50 figure 3-5. memory map ( pd78f9479) f 7 0 0 h f 6 f f h special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits f f f f h f f 0 0 h f e f f h f b 0 0 h f a f f h 0 0 0 0 h program memory space data memory space b f f f h 0 0 0 0 h program area 0 0 8 0 h 0 0 7 f h program area 0 0 4 0 h 0 0 3 f h callt table area reserved 0 0 3 0 h 0 0 2 f h vector table area flash memory 49,152 8 bits f a 1 c h f a 1 b h f a 0 0 h f 9 f f h reserved reserved internal low-speed ram 512 8 bits f 5 0 0 h f 4 f f h c 0 0 0 h b f f f h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 51 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). internal rom (or flash memory) with the following capacity is provided for each product in the pd789478 subseries. table 3-1. internal rom capacity internal rom part number structure capacity pD789477 24,576 8 bits pd789478 32,768 8 bits pd789479 note mask rom 49,152 8 bits pd78f9478 32,768 8 bits pd78f9479 note flash memory 49,152 8 bits note under development the following areas are allocated to the internal program memory space. (1) vector table area the 46-byte area of addresses 0000h to 002dh in the pD789477, 789478, and 78f9478 and the 48-byte area of addresses 0000h to 002fh in the pd789479 and 78f9479 is reserved as a vector table area. this area stores program start addresses to be used when branching by reset input or interrupt request generation. of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0018h inttm20 0004h intwdt 001ah inttm50 0006h intp0 001ch inttm60 0008h intp1 001eh inttm61 000ah intp2 0020h intad0 000ch intp3 0022h intwt 000eh intrin 0024h intkr00 0010h intsr20/intcsi20 0026h intrerr 0012h intcsi10 0028h intgp 0014h intst20 002ah intrend 0016h intwti 002ch intdfull 002eh intkr01 note note pd789479 and 78f9479 only (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 52 3.1.2 internal data memory space (1) internal high-speed ram and internal low-speed ram the pd789478 subseries products incorporate internal high-speed ram and internal low-speed ram of the following capacity for each product. the internal high-speed ram can also be used as a stack. the internal low-speed ram cannot be used as a stack. table 3-3. internal high-speed ram, internal low-speed ram capacity part number structure capacity pD789477 768 8 bits ? pd789478 1,024 8 bits pd789479 note 512 8 bits pd78f9478 ? pd78f9479 note 512 8 bits note under development (2) lcd display ram lcd display ram is incorporated in the area between fa00h and fa1bh. the lcd display ram can also be used as ordinary ram. 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocated in the area between ff00h and ffffh (see table 3-4 ). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 53 3.1.4 data memory addressing the pd789478 subseries is provided with a variety of addressing modes to make memory manipulation as efficient as possible. at the addresses corresponding to data memory area especially, specific addressing modes that correspond to the particular function of an area such as the special function registers are available. figures 3-6 to 3-10 show the data memory addressing modes. figure 3-6. data memory addressing ( pD789477) special function registers 256 8 bits internal high-speed ram 768 8 bits lcd display ram 28 4 bits f f f f h 6 0 0 0 h 5 f f f h 0 0 0 0 h direct addressing register indirect addressing based addressing f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h sfr addressing short direct addressing f c 0 0 h f b f f h f a 1 c h f a 1 b h reserved f a 0 0 h f 9 f f h reserved internal rom 24,576 8 bits www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 54 figure 3-7. data memory addressing ( pd789478) special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits f f f f h 8 0 0 0 h 7 f f f h 0 0 0 0 h direct addressing register indirect addressing based addressing f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h sfr addressing short direct addressing f b 0 0 h f a f f h f a 1 c h f a 1 b h reserved f a 0 0 h f 9 f f h reserved internal rom 32,768 8 bits www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 55 figure 3-8. data memory addressing ( pd78f9478) special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits f f f f h 8 0 0 0 h 7 f f f h 0 0 0 0 h direct addressing register indirect addressing based addressing f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h sfr addressing short direct addressing f b 0 0 h f a f f h f a 1 c h f a 1 b h reserved f a 0 0 h f 9 f f h reserved flash memory 32,768 8 bits www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 56 figure 3-9. data memory addressing ( pd789479) special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits internal low-speed ram 512 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved reserved reserved internal rom 49,152 8 bits f f f f h 0 0 0 0 h f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h f b 0 0 h f a f f h f a 1 c h f a 1 b h f a 0 0 h f 9 f f h f 7 0 0 h f 6 f f h f 5 0 0 h f 4 f f h c 0 0 0 h b f f f h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 57 figure 3-10. data memory addressing ( pd78f9479) special function registers 256 8 bits internal high-speed ram 1,024 8 bits lcd display ram 28 4 bits internal low-speed ram 512 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved reserved reserved flash memory 49,152 8 bits f f f f h 0 0 0 0 h f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h f b 0 0 h f a f f h f a 1 c h f a 1 b h f a 0 0 h f 9 f f h f 7 0 0 h f 6 f f h f 5 0 0 h f 4 f f h c 0 0 0 h b f f f h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 58 3.2 processor registers the pd789478 subseries is provided with the following on-chip processor registers. 3.2.1 control registers the control registers contain special functions to control the program sequence status and stack memory. the program counter, program status word, and stack pointer are control registers. (1) program counter (pc) the program counter is a 16-bit register that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data or register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the pc. figure 3-11. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. the program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically restored upon execution of the reti and pop psw instructions. reset input sets psw to 02h. figure 3-12. program status word configuration 70 ie z0ac001cy psw www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 59 (a) interrupt enable flag (ie) this flag controls interrupt request acknowledgement operations of the cpu. when 0, ie is set to the interrupt disabled status (di), and interrupt requests other than non-maskable interrupts are all disabled. when 1, ie is set to the interrupt enabled status (ei). interrupt request acknowledgement enable is controlled by the interrupt mask flag for the corresponding interrupt source. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores an overflow or underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 60 (3) stack pointer (sp) this is a 16-bit register that holds the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-13. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 3-14 and 3-15. caution since reset input makes the sp contents undefined, be sure to initialize the sp before instruction execution. figure 3-14. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 higher register pairs figure 3-15. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs ret instruction pop rp instruction sp pc7 to pc0 higher register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 61 3.2.2 general-purpose registers the general-purpose registers consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). general-purpose registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, or hl) or absolute names (r0 to r7 and rp0 to rp3). figure 3-16. general-purpose register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 62 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. the special function registers are allocated in the 256-byte area of ff00h to ffffh. special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions. the manipulatable bit units (1, 8, and 16) differ depending on the special function register type. the manipulatable bits can be specified as follows. 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand. when addressing an address, describe an even address. table 3-4 lists the special function registers. the meanings of the symbols in this table are as follows. symbol indicates the addresses of the incorporated special function registers. the symbols shown in this column are the reserved words in the assembler, and have already been defined in the header file ? sfrbit.h ? in the c compiler. therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. r/w indicates whether the special function register in question can be read or written. r/w: read/write r: read only w: write only bit unit for manipulation indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated. after reset indicates the status of the special function register when the reset signal is input. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 63 table 3-4. special function registers (1/3) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ?? ff01h port 1 p1 ?? ff02h port 2 p2 ?? ff03h port 3 p3 ?? ff05h port 5 p5 r/w ?? ff06h port 6 p6 ?? ff07h port 7 note p7 r ?? ff08h port 8 note p8 r/w ?? 00h ff0ah 8-bit compare register 61 cr61 w ?? undefined ff0bh 8-bit timer counter 61 tm61 r ?? 00h ff0ch 8-bit compare register 60 cr60 ? ff0dh 8-bit compare register 50 cr50 cr6 w ? undefined ff0eh 8-bit timer counter 60 tm60 ? ff0fh 8-bit timer counter 50 tm50 tm6 r ? ff11h serial i/o shift register 1a0 sio1a0 r/w ?? 00h ff12h 16-bit multiplication result store register l mul0l ? ff13h 16-bit multiplication result store register h mul0h mul 0 ? undefined ff15h a/d conversion result register 0 adcrl0 r ?? 00h ff16h ff17h 16-bit compare register 20 cr20 w ?? ffffh ff18h ff19h 16-bit timer counter 20 tm20 ?? 0000h ff1ah ff1bh 16-bit capture register 20 tcp20 r ?? undefined ff20h port mode register 0 pm0 ?? ff21h port mode register 1 pm1 ?? ff22h port mode register 2 pm2 ?? ff23h port mode register 3 pm3 ?? ff25h port mode register 5 pm5 ?? ff28h port mode register 8 note pm8 ?? ffh ff30h pull-up resistor option register b0 pub0 ?? ff31h pull-up resistor option register b1 pub1 ?? ff32h pull-up resistor option register b2 pub2 ?? ff33h pull-up resistor option register b3 pub3 r/w ?? 00h ff40h 8-bit h width compare register 61 crh61 w ?? undefined ff41h 8-bit timer mode control register 61 tmc61 ?? ff42h watchdog timer clock selection register wdcs r/w ?? 00h ff46h subclock selection register note ssck ?? note when used as a port by a mask option or port function register. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 64 table 3-4. special function registers (2/3) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff48h 16-bit timer mode control register 20 tmc20 ?? ff4ah watch timer mode control register wtm ?? ff4bh watch timer interrupt time selection register wtim r/w ?? 00h ff4ch 8-bit h width compare register 60 crh60 w ?? undefined ff4dh 8-bit timer mode control register 50 tmc50 ?? ff4eh 8-bit timer mode control register 60 tmc60 ?? ff4fh carrier generator output control register 60 tca60 r/w ?? ff57h port function register 7 note pf7 ?? ff58h port function register 8 note pf8 w ?? ff60h remote controller receive control register rmcn r/w ?? ff61h remote controller receive data register rmdr ?? ff62h remote controller shift register receive counter register rmscr ?? ff63h remote controller receive shift register rmsr r ?? ff64h remote controller receive gpls compare register rmgpls ?? ff65h remote controller receive gpll compare register rmgpll ?? ff66h remote controller receive gphs compare register rmgphs ?? ff67h remote controller receive gphl compare register rmgphl ?? ff68h remote controller receive dls compare register rmdls ?? ff69h remote controller receive dll compare register rmdll ?? ff6ah remote controller receive dh0s compare register rmdh0s ?? ff6bh remote controller receive dh0l compare register rmdh0l ?? ff6ch remote controller receive dh1s compare register rmdh1s ?? ff6dh remote controller receive dh1l compare register rmdh1l ?? ff6eh remote controller receive end width selection register rmer ?? ff70h asynchronous serial interface mode register 20 asim20 r/w ?? ff71h asynchronous serial interface status register 20 asis20 r ?? ff72h serial operation mode register 20 csim20 ?? ff73h baud rate generator control register 20 brgc20 r/w ?? 00h transmit shift register 20 txs20 w ?? ffh ff74h receive buffer register 20 rxb20 sio20 r ?? undefined ff78h serial operation mode register 1a0 csim1a0 ?? ff79h automatic data transmit/receive control register 0 adtc0 ?? 00h ff7ah automatic data transmit/receive address pointer 0 adtp0 r/w ?? undefined ff7bh automatic data transmit/receive interval specification register 0 adti0 ?? 00h note these registers function only in the pd78f9478 and 78f9479; however, writing to these registers in the pD789477, 789478, and 789479 will not affect the operation. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 65 table 3-4. special function registers (3/3) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff80h a/d converter mode register 0 adml0 ?? ff81h a/d converter mode register 1 adml1 ?? ff84h analog input channel specification register 0 ads0 ?? 00h ffa0h serial interface buffer memory 0 sbmem0 ?? ffa1h serial interface buffer memory 1 sbmem1 ?? ffa2h serial interface buffer memory 2 sbmem2 ?? ffa3h serial interface buffer memory 3 sbmem3 ?? ffa4h serial interface buffer memory 4 sbmem4 ?? ffa5h serial interface buffer memory 5 sbmem5 ?? ffa6h serial interface buffer memory 6 sbmem6 ?? ffa7h serial interface buffer memory 7 sbmem7 ?? ffa8h serial interface buffer memory 8 sbmem8 ?? ffa9h serial interface buffer memory 9 sbmem9 ?? ffaah serial interface buffer memory a sbmema ?? ffabh serial interface buffer memory b sbmemb ?? ffach serial interface buffer memory c sbmemc ?? ffadh serial interface buffer memory d sbmemd ?? ffaeh serial interface buffer memory e sbmeme ?? ffafh serial interface buffer memory f sbmemf ?? undefined ffb0h lcd display mode register 0 lcdm0 ?? ffb2h lcd clock control register 0 lcdc0 r/w ?? 00h ffd0h multiplication data register a0 mra0 ?? ffd1h multiplication data register b0 mrb0 w ?? undefined ffd2h multiplier control register 0 mulc0 ?? ffe0h interrupt request flag register 0 if0 ?? ffe1h interrupt request flag register 1 if1 ?? ffe2h interrupt request flag register 2 if2 ?? 00h ffe4h interrupt mask flag register 0 mk0 ?? ffe5h interrupt mask flag register 1 mk1 ?? ffe6h interrupt mask flag register 2 mk2 ?? ffh ffech external interrupt mode register 0 intm0 ?? ffedh external interrupt mode register 1 intm1 ?? fff0h subclock oscillation mode register sckm ?? fff2h subclock control register css ?? fff4h key return mode register 01 note krm01 ?? fff5h key return mode register 00 krm00 ?? fff9h watchdog timer mode register wdtm ?? 00h fffah oscillation stabilization time selection register osts ?? 04h fffbh processor clock control register pcc r/w ?? 02h note pd789479, 78f9479 only www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 66 3.3 instruction address addressing an instruction address is determined by the program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two ? s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. this means that information is relatively branched to a location between ? 128 and +127, from the start address of the next instruction when relative addressing is used. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits 0. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits 1. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 67 3.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 instruction is executed. call !addr16 and br !addr16 instructions can be branched to any location in the memory space. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 68 3.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. the instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4 ? 0 instruction code 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 69 3.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated with immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 00101001op code 00000000 11111110 00h feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory ? ? ? ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 70 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the whole sfr area. ports that are frequently accessed in a program and the compare register of the timer/event counter are mapped in this area, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1110101 10010000 01010000 op code 90h (saddr-offset) 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 71 3.4.3 special function register (sfr) addressing [function] the memory-mapped special function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 256-byte space ff00h to ffffh. however, the sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 72 3.4.4 register addressing [function] in the register addressing mode, general-purpose registers are accessed as operands. the general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 00001010 00100101 register specification code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specification code www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 73 3.4.5 register indirect addressing [function] in the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. the register pair to be accessed is specified by the register pair specification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 00101011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de addressed memory contents are transferred. memory address specified with register pair de. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 3 cpu architecture user ? s manual u15400ej3v0ud 74 3.4.6 based addressing [function] 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 00101101 00010000 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. only the internal high-speed ram area can be addressed using stack addressing. [description example] in the case of push de instruction code 10101010 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 75 chapter 4 port functions 4.1 port functions the pd789478 subseries provides the ports shown in figure 4-1, enabling various methods of control. the functions of each port are shown in table 4-1. numerous other functions are provided that can be used in addition to the digital i/o port functions. for more information on these additional functions, see chapter 2 pin functions . figure 4-1. port types p50 p00 port 0 port 5 p53 p07 p25 port 6 p60 p67 p10 port 1 p11 port 2 p20 p34 port 3 p30 p70 port 7 p73 port 8 p80 p87 remark ports 7 and 8 are used when the port function is selected by a mask option or port function register. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 76 table 4-1. port functions port name pin name function port 0 p00 to p07 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b0 (pub0) or the key return mode register (krm00). port 1 p10, p11 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b1 (pub1). port 2 p20 to p25 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b2 (pub2). port 3 p30 to p34 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register b3 (pub3). port 5 p50 to p53 n-ch open-drain i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by mask option. port 6 p60 to p67 input port port 7 p70 to p73 input port (only when input port is selected by mask option or port function register) port 8 p80 to p87 i/o port (only when i/o port is selected by mask option) notes 1. whether to use these pins as input port pins (p70 to p73) or segment outputs (s16 to s19) can be selected in 1-bit units by means of a mask option in the pD789477, 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 2. whether to use these pins as i/o port pins (p80 to p87) or segment outputs (s20 to s27) can be selected in 1-bit units by means of a mask option in the pD789477, 789478, and 789479 or a port mode register in the pd78f9478 and 78f9479 (refer to 4.3 (3) port function registers and chapter 20 mask options ). 4.2 port configuration ports have the following hardware configuration. table 4-2. configuration of port item configuration control registers port mode registers (pmm: m = 0 to 3, 5, 8) pull-up resistor option registers (pub0 to pub3) port function registers (pf7, pf8) (flash memory version only) ports total: 45 (cmos i/o: 29, cmos input: 12, n-ch open-drain i/o: 4) pull-up resistors ? mask rom version total: 25 (software control: 21, mask option specification: 4) ? flash memory version total: 21 (software control only) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 77 4.2.1 port 0 this is an 8-bit i/o port with an output latch. port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (pm0). when the p00 to p07 pins are used as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b0 (pub0). this port is also used for key return signal input. reset input sets port 0 to input mode. figure 4-2 shows a block diagram of port 0. figure 4-2. block diagram of p00 to p07 krm00: key return mode register 00 pub0: pull-up resistor option register b0 pm: port mode register rd: port 0 read signal wr: port 0 write signal notes 1. pD789477, 789478, and 78f9478 only 2. pd789479 and 78f9479 only wr krm00 v dd p00/kr0 to p07/kr7 note 1 or p00/kr00 to p07/kr07 note 2 wr puo rd wr port w rpm pub00 to pub07 pm00 to pm07 krm000, krm004 to krm007 p-ch internal bus selector output latch (p00 to p07) alternate function www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 78 4.2.2 port 1 this is a 2-bit i/o port with an output latch. port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (pm1). when using the p10 and p11 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b1 (pub1). reset input sets this port to input mode. figure 4-3 shows a block diagram of port 1. figure 4-3. block diagram of p10 and p11 wr pu0 rd wr port wr pm pub10, pub11 pm10, pm11 v dd p-ch p10, p11 internal bus selector output latch (p10, p11) pub1: pull-up resistor option register b1 pm: port mode register rd: port 1 read signal wr: port 1 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 79 4.2.3 port 2 this is a 6-bit i/o port with an output latch. port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (pm2). when using the p20 to p25 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b2 (pub2). this port is also used for serial interface i/o. reset input set this port to input mode. figures 4-4 to 4-8 show block diagrams of port 2. caution when using the pins of port 2 as the serial interface, the i/o or output latch must be set according to the function to be used. for how to set the latches, see table 11-2 serial interface 20 operation mode settings and 12.3 (1) serial operation mode register 1a0 (csim1a0). figure 4-4. block diagram of p20 internal bus v dd p-ch p20/asck20/ sck20 wr pub2 rd wr port wr pm pub20 alternate function output latch (p20) pm20 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 80 figure 4-5. block diagram of p21 internal bus v dd p21/so20/txd20 wr pub2 rd wr port wr pm pub21 alternate function output latch (p21) pm21 selector p-ch pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 81 figure 4-6. block diagram of p22 and p25 p22/si20/ rxd20, p25/si10 wr pub2 rd wr port wr pm pub22, pub25 alternate function output latch (p22, p25) pm22, pm25 v dd p-ch internal bus selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 82 figure 4-7. block diagram of p23 internal bus v dd p-ch p23/sck10 wr pub2 rd wr port wr pm pub23 alternate function output latch (p23) pm23 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 83 figure 4-8. block diagram of p24 internal bus v dd p24/so10 wr pub2 rd wr port wr pm pub24 alternate function output latch (p24) pm24 selector p-ch pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 84 4.2.4 port 3 this is a 5-bit i/o port with an output latch. port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (pm3). when using the p30 to p34 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b3 (pub3). this port is also used as an external interrupt input, capture input, timer i/o, and remote control receive data input. reset input sets this port to input mode. figures 4-9 and 4-10 show block diagrams of port 3. figure 4-9. block diagram of p30 to p33 pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal p30/intp0/to50/ tmi60, p31/intp1/to60, p32/intp2/to61/ tmi61 p33/intp3/to20/ cpt20 wr pub3 rd wr port wr pm pub30 to pub33 pm30 to pm33 v dd p-ch internal bus alternate function selector output latch (p30 to p33) alternate function www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 85 figure 4-10. block diagram of p34 pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal p34/rin wr pub3 rd wr port wr pm pub34 pm34 v dd p-ch internal bus selector output latch (p34) alternate function www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 86 4.2.5 port 5 this is a 4-bit n-ch open-drain i/o port with an output latch. port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, use of an on-chip pull-up resistor can be specified by a mask option. reset input sets this port to input mode. figure 4-11 shows a block diagram of port 5. figure 4-11. block diagram of p50 to p53 pm: port mode register rd: port 5 read signal wr: port 5 write signal internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd mask option resistor mask rom version only. for a flash memory version, a pull-up resistor is not incorporated. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 87 4.2.6 port 6 this is an 8-bit input-only port. this port is also used for the analog input of an a/d converter and of key return signal input . figure 4-12 shows a block diagram of port 6. note pd789479 and 78f9479 only figure 4-12. block diagram of p60 to p67 (1/2) (a) pD789477, 789478, and 78f9478 v ref rd a/d converter p60/ani0 to p67/ani7 + ? internal bus rd: port 6 read signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 88 figure 4-12. block diagram of p60 to p67 (2/2) (b) pd789479 and 78f9479 krm01: key return mode register 01 rd: port 6 read signal internal bus v ref rd a/d converter p60/ani0/kr10 to p67/ani7/kr17 + ? wr krm01 krm010, krm014 to krm017 alternate function www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 89 4.2.7 port 7 this is a 4-bit input-only port. only the bits for which the port function is selected can be used, by using a mask option in the pD789477, 789478, and 789479 or port function register 7 (pf7) in the pd78f9478 and 78f9479. figure 4-13 shows a block diagram of port 7. figure 4-13. block diagram of p70 to p73 p70 to p73 rd internal bus rd: port 7 read signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 90 4.2.8 port 8 this is an 8-bit i/o port with an output latch. only the bits for which the port function is selected can be used, by using a mask option in the pD789477, 789478, and 789479 or port function register 8 (pf8) in the pd78f9478 and 78f9479. port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (pm8). reset input set this port to input mode. figure 4-14 shows a block diagram of port 8. figure 4-14. block diagram of p80 to p87 rd wr port wr pm output latch (p80 to p87) pm80 to pm87 p80 to p87 internal bus selector pm: port mode register rd: port 8 read signal wr: port 8 write signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 91 4.3 registers controlling port function the ports are controlled by the following three types of registers. ? port mode registers (pm0 to pm3, pm5, pm8) ? pull-up resistor option registers (pub0 to pub3) ? port function registers (pf7, pf8) ( pd78f9478 and 78f9479 only) (1) port mode registers (pm0 to pm3, pm5, pm8) input and output can be specified in 1-bit units. these registers can be set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when using the port pins as their alternate functions, set the port mode register and the output latch as shown in table 4-3. caution because p30 to p33 function alternately as external interrupt inputs, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0 to pmk3) before using the port in output mode. figure 4-15. port mode register format symbol76543210addressafter resetr/w pm0 pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 ff20h ffh r/w pm1111111pm11pm10ff21hffhr/w pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 ff22h ffh r/w pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 ff23h ffh r/w pm5 1 1 1 1 pm53 pm52 pm51 pm50 ff25h ffh r/w pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 ff28h ffh r/w pmmn pmn pin input/output mode selection (m = 0 to 3, 5, 8, n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) remark pm8 can only be used when one of pins p80 to p87 is selected as a port function pin by a mask option or port function register 8 (pf8). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 92 table 4-3. port mode registers and output latch settings when using alternate functions alternate function pin name name i/o pm p p00 to p07 kr0 to kr7 or kr00 to kr07 input 1 intp0 input 1 to50 output 0 0 p30 tmi60 input 1 intp1 input 1 p31 to60 output 0 0 intp2 input 1 tmi61 input 1 p32 to61 output 0 0 intp3 input 1 cpt20 input 1 p33 to20 output 0 0 p34 rin input 1 remark : don ? t care pm : port mode register p : port output latch caution when port 2 is used for the serial interface, i/o and output latch settings must be made in accordance with the function used. for the setting method, refer to table 11-2 serial interface 20 operation mode settings and 12.3 (1) serial operation mode register 1a0 (csim1a0). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 93 (2) pull-up resistor option registers (pub0 to pub3) these registers set whether to use on-chip pull-up resistors for pins p00 to p07, p10, p11, p20 to p25, and p30 to p34. an on-chip pull-up resistor can be used only for those bits set to the input mode in a port for which the use of the on-chip pull-up resistor has been specified using pub0 to pub3. for those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of pub0 to pub3. this also applies to alternate-function pins used as output pins. pub0 to pub3 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 4-16. format of pull-up resistor option registers symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w pub0 pub07 pub06 pub05 pub04 pub03 pub02 pub01 pub00 ff30h 00h r/w 765432<1><0> pub1000000pub11pub10ff31h00hr/w 7 6 <5> <4> <3> <2> <1> <0> pub2 0 0 pub25 pub24 pub23 pub22 pub21 pub20 ff32h 00h r/w 7 6 5 <4> <3> <2> <1> <0> pub3 0 0 0 pub34 pub33 pub32 pub31 pub30 ff33h 00h r/w pubmn pmn on-chip pull-up resistor selection (m = 0 to 3, n = 0 to 7) 0 an on-chip pull-up resistor is not connected. 1 an on-chip pull-up resistor is connected. (3) port function registers (pf7 and pf8) ( pd78f9478 and 78f9479 only) these registers specify in 1-bit units whether to use p70 to p73 and p80 to p87 as ports or segment outputs. pf7 and pf8 are set with 8-bit memory manipulation instruction. reset input sets these registers to 00h. caution this register is valid only in the pd78f9478 and 78f9479; however, writing to it in the pD789477, 789478, and 789479 will simply make it invalid, causing no operational effect. figure 4-17. port function register format symbol7654<3><2><1><0>addressafter resetr/w pf7 0 0 0 0 pf73 pf72 pf71 pf70 ff57h 00h w <7> <6> <5> <4> <3> <2> <1> <0> pf8 pf87 pf86 pf85 pf84 pf83 pf82 pf81 pf80 ff58h 00h w pfmn pmn port/segment output specification (m = 7 or 8, n = 0 to 7) 0 pmn is used as a port pin. 1 pmn is used as a segment output. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 4 port functions user ? s manual u15400ej3v0ud 94 4.4 port function operation the operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port by using a transfer instruction. the contents of the output latch can be output from the pins of the port. once data written to the output latch, it is retained until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a transfer instruction. however, the status of the port pin is not changed because the output buffer is off. once data written to the output latch, it is retained until new data is written to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the status of an output latch can be read by using a transfer instruction. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed on the contents of the output latch. the result of the operation is written to the output latch. the contents of the output latch are output from the port pins. once data written to the output latch, it is retained until new data is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 95 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. ? ? ? ? main system clock oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). ? ? ? ? subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by the suboscillation mode register (sckm). also, a circuit to multiply the subsystem clock by 4 can be used by setting a mask option or the subclock selection register (ssck). 5.2 clock generator configuration the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers processor clock control register (pcc) subclock oscillation mode register (sckm) subclock control register (css) subclock selection register (ssck) ( pd78f9478 and 78f9479 only) oscillators main system clock oscillator subsystem clock oscillator www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user?s manual u15400ej3v0ud 96 figure 5-1. clock generator block diagram ( pD789477, 789478, and 789479) subsystem clock oscillator f xt 8f xt f xtt 4f xt x1 x2 xt1 xt2 main system clock oscillator f x f x 2 2 f xtt 2 1/2 prescaler timer 50 watch timer lcd controller/driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus subclock oscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) 4 multiplication circuit mask option mask option 2 multiplication circuit a/d converter remark f xtt :f xt or 8f xt www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 97 figure 5-2. clock generator block diagram ( pd78f9478, 78f9479) subsystem clock oscillator f xt x1 x2 xt1 xt2 main system clock oscillator f x f x 2 2 f xtt 2 1/2 prescaler timer 50 watch timer lcd controller/driver a/d converter clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus subclock oscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) 8f xt f xtt 4f xt selector subclock selection register (ssck) sct 4 multiplication circuit 2 multiplication circuit remark f xtt :f xt or 8f xt www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 98 5.3 registers controlling clock generator the clock generator is controlled by the following four registers. ? processor clock control register (pcc) ? subclock oscillation mode register (sckm) ? subclock control register (css) ? subclock selection register (ssck) ( pd78f9478 and 78f9479 only) (1) processor clock control register (pcc) this register is used to select the cpu clock and set the frequency division ratio. pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 02h. figure 5-3. format of processor clock control register symbol <7> 6 5 4 3 2 <1> 0 address after reset r/w pcc mcc 0 0 0 0 0 pcc1 0 fffbh 02h r/w mcc main system clock oscillator operation control 0 operation enabled 1 operation stopped minimum instruction execution time: 2/f cpu css0 pcc1 cpu clock (f cpu ) selection note f x = 5.0 mhz or f xt = 32.768 khz 00f x 0.4 s 01 f x /2 2 1.6 s 1 f xt /2 4f xt (when 4 multiplication circuit is used) 122 s 15.26 s (when 4 multiplication circuit is used) note the cpu clock is selected by a combination of flag settings in the pcc and css registers. (refer to 5.3 (3) subclock control register (css) .) cautions 1. always set bits 0 and 2 to 6 to 0. 2. mcc can be set only when the subsystem clock is selected as the cpu clock. setting mcc to 1 while the main system clock is operating is invalid. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 99 (2) subclock oscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sckm to 00h. figure 5-4. format of subclock oscillation mode register feedback resistor selection note 000000frcscc sckm symbol address after reset r/w fff0h 00h r/w 7654321<0> frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. when only the subclock is not used, the power consumption in stop mode can be further reduced by setting frc = 1. caution bits 2 to 7 must be set to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 100 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies the cpu clock operation status. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets css to 00h. figure 5-5. format of subclock control register cpu clock operation status 0 0 cls css0 0000 css address after reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the (divided) main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 (divided) output from the main system clock oscillator output from the subsystem clock oscillator symbol note note bit 5 is read only. caution bits 0 to 3, 6, and 7 must be set to 0. (4) subclock selection register (ssck) ( pd78f9478 and 78f9479 only) this register is used to control the operation of the 4 subsystem clock multiplication circuit. ssck is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. caution this register is valid only in the pd78f9478 and 78f9479; however, writing to it in the pD789477, 789478, and 789479 will simply make it invalid, causing no operational effect. figure 5-6. format of subclock selection register symbol76543210addressafter resetr/w ssck0000000sctff46h retained note r/w sct control of 4 subsystem clock multiplication circuit 0 operation disabled (subsystem clock source (32. 768 khz) supplied to the cpu) 1 operation enabled (clock that is the sub system clock multiplied by 8 ( 262 khz) supplied to the cpu) note the register is set to 00h only by reset input. cautions 1. always set bits 1 to 7 to 0. 2. write to the sct flag prior to setting the css0 flag to 1 following the release of reset. write operations following the first operation are invalid (input the reset signal to rewrite). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 101 5.4 system clock oscillators 5.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-7 shows the external circuit of the main system clock oscillator. figure 5-7. external circuit of main system clock oscillator (a) crystal or ceramic oscillation (b) external clock crystal or ceramic resonator v ss x2 x1 external clock x1 x2 caution when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in figure 5-7 to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 102 5.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the crystal resonator (32.768 khz typ.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 5-8 shows the external circuit of the subsystem clock oscillator. figure 5-8. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 ic (v pp ) xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in figures 5-7 and 5-8 to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. when using the subsystem clock, particular care is required because the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 103 5.4.3 example of incorrect resonator connection figure 5-9 shows examples of incorrect resonator connection. figure 5-9. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 port (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to xt2 in series. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 104 figure 5-9. examples of incorrect resonator connection (2/2) (e) signal is fetched v ss x1 x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, respectively, and connect a resistor to xt2 in series. 5.4.4 divider circuit the divider circuit divides the output of the main system clock oscillator (f x ) to generate various clocks. 5.4.5 when subsystem clock is not used if the subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the xt1 and xt2 pins as follows. xt1: connect to v ss xt2: leave open in this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the subclock oscillation mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above. 5.4.6. subsystem clock 4 multiplication circuit this circuit multiplies the subsystem clock by 4 and supplies it to the cpu. the circuit stops operations in the halt mode (to reduce power consumption). when the circuit starts operating after the halt mode is released, a one-clock wait of the original subsystem clock is inserted to eliminate noise. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 105 5.5 clock generator operation the clock generator generates the following clocks and controls the operation modes of the cpu, such as the standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation and function of the clock generator is determined by the processor clock control register (pcc), subclock oscillation mode register (sckm), and subclock control register (css), as follows. (a) the low-speed mode (1.6 s: at 5.0 mhz operation) of the main system clock is selected when the reset signal is generated (pcc = 02h). while a low level is being input to the reset pin, oscillation of the main system clock is stopped. (b) three types of minimum instruction execution time (0.4 s and 1.6 s: main system clock (at 5.0 mhz operation), 122 s: subsystem clock (at 32.768 khz operation)) can be selected by the pcc, sckm, and css settings. also, the subsystem clock can be changed to a clock that uses a circuit to multiply the subclock by 4 via a mask option in the pD789477, 789478, and 789479 or the subclock selection register (ssck) in the pd78f9478 and 78f9479 (15.26 s: a circuit to multiply the subsystem clock by 4 is used). (c) two standby modes, stop and halt, can be used with the main system clock selected. in a system where the subsystem clock is not used, setting bit 1 (frc) of sckm so that the on-chip feedback resistor cannot be used reduces power consumption in stop mode. in a system where the subsystem clock is used, setting sckm bit 0 to 1 can cause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsystem clock so that low power consumption operation is used (122 s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possible to cause the main system clock to stop oscillating using bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock, but the subsystem clock pulse is only supplied to 8-bit timer 50, the watch timer, and the lcd controller/driver. 8-bit timer 50, the watch timer, and the lcd controller/driver can therefore keep running even during standby. the other hardware stops when the main system clock stops because it runs based on the main system clock (except for external input clock operations). because the subsystem clock pulse is supplied to the a/d converter via the 4 multiplication circuit, the a/d converter cannot be used during standby. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 106 5.6 changing setting of system clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the setting of pcc has been changed; the old clock is used for the duration of several instructions after that (see table 5-2 ). table 5-2. maximum time required for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 00011 0 4 clocks 2f x /f xt clocks (306 clo cks) 0 1 2 clocks f x /2f xt clocks (76 clocks) 1 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execution time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. : don ? t care www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 5 clock generator user ? s manual u15400ej3v0ud 107 5.6.2 switching between system clock and cpu clock the following figure illustrates how the cpu clock and system clock switch. figure 5-10. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f x f x f xt f x low-speed operation high-speed operation subsystem clock operation high-speed operation wait (6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on power application. the effect of resetting is released when the reset pin is later made high, and the main system clock starts oscillating. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts instruction execution at the slow speed of the main system clock (1.6 s: at 5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that high-speed operation can be selected. <3> a drop of the v dd voltage is detected with an interrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status). <4> a recover of the v dd voltage is detected with an interrupt request signal. bit 7 (mcc) of pcc is set to 0, and then the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so that high-speed operation can be selected again. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 108 chapter 6 16-bit timer 20 6.1 16-bit timer 20 functions 16-bit timer 20 has the following functions. ? timer interrupt ? timer output ? count value capture (1) timer interrupt an interrupt is generated when a count value and compare value match. (2) timer output timer output can be controlled when a count value and compare value match. (3) count value capture the count value of 16-bit timer counter 20 (tm20) is latched into a capture register in synchronization with the capture trigger and retained. 6.2 16-bit timer 20 configuration 16-bit timer 20 includes the following hardware. table 6-1. 16-bit timer 20 configuration item configuration timer counters 16 bits 1 (tm20) registers compare register: 16 bits 1 (cr20) capture register: 16 bits 1 (tcp20) timer outputs 1 (to20) control registers 16-bit timer mode control register 20 (tmc20) port mode register 3 (pm3) port 3 (p3) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user?s manual u15400ej3v0ud 109 figure 6-1. block diagram of 16-bit timer 20 cpt20/to20 /intp3/p33 internal bus internal bus 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 f x f x /2 2 edge detector 16-bit capture register 20 (tcp20) 16-bit counter read buffer 16-bit timer counter 20 (tm20) 16-bit compare register 20 (cr20) match ovf f/f tod20 to20/cpt20 /intp3/p33 inttm20 p33 output latch pm33 f x /2 5 timer 61 interrupt request signal selector (1) 16-bit compare register 20 (cr20) this 16-bit register is used to continually compare the value set to cr20 with the count value in 16-bit timer counter 20 (tm20) and to issue an interrupt request (inttm20) when a match occurs. cr20 is set with a 16-bit memory manipulation instruction. values from 0000h to ffffh can be set. reset input sets this register to ffffh. caution to rewrite cr20 during a count operation, first disable interrupts by setting interrupt mask flag register 0 (mk0). also, set inversion inhibited for the timer output data in 16-bit timer mode control register 20 (tmc20). if the value in cr20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 20 (tm20) this is a 16-bit register that is used to count the count pulses. tm20 can be read with a 16-bit memory manipulation instruction. the counter is in free-running mode when the count clock is being input. reset input sets this counter to 0000h and restarts free-running mode. caution the count value after releasing stop mode is undefined because the count operation occurred during the oscillation stabilization time. (3) 16-bit capture register 20 (tcp20) this is a 16-bit register used to capture the contents of 16-bit timer counter 20 (tm20). tcp20 is set with a 16-bit memory manipulation instruction. reset input makes this register undefined. (4) 16-bit counter read buffer 20 this buffer is used to latch and hold the count value for tm20. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 110 6.3 registers controlling 16-bit timer 20 16-bit timer 20 is controlled by the following three registers. ? 16-bit timer mode control register 20 (tmc20) ? port mode register 3 (pm3) ? port 3 (p3) (1) 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 (tmc20) controls the setting of the count clock, capture edge, etc. tmc20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc20 to 00h. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 111 figure 6-2. format of 16-bit timer mode control register 20 symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc20 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 ff48h 00h r/w note 1 tod20 timer output data 0 timer output is ? 0 ? 1 timer output is ? 1 ? tof20 set overflow flag 0 reset and clear by software 1 set by overflow of 16-bit timer cpt201 cpt200 selection of capture edge 0 0 capture operation disabled 0 1 rising edge of cpt20 pin 1 0 falling edge of cpt20 pin 1 1 both edges of cpt20 pin toc20 timer output data inversion control 0 inversion disabled 1 inversion enabled tcl201 tcl200 selection of count clock for 16-bit timer counter 20 0 0 timer 61 interrupt signal 01f x (5.0 mhz) notes 2, 3 10 f x /2 2 (1.25 mhz) note 4 11 f x /2 5 (156.25 khz) note 4 toe20 output control for 16-bit timer counter 20 0 output disabled (port mode) 1 output enabled notes 1. bit 7 is read-only. 2. if f x is selected for the count clock, the signal cannot be used as a capture signal. 3. in a read operation, set the cpu clock as the high-speed main clock (pcc1 = 0, css = 0). 4. in a read operation, set the cpu clock as the main clock (css = 0). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 112 (2) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. when using the p33/intp3/cpt20/to20 pin as a capture input (cpt20), set pm33 to 1. when using the above pin as a timer output (to20), set the pm33 and p33 output latches to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 6-3. format of port mode register 3 symbol76543210addressafter resetr/w pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 ff23h ffh r/w pm33 selection of p33 pin i/o mode 0 output mode (output buffer is on) 1 input mode (output buffer is off) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 113 6.4 16-bit timer 20 operation 6.4.1 operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set to cr20. since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is equal to one cycle of the count clock set in tcl201 and tcl200. to operate 16-bit timer 20 as a timer interrupt, the following settings are required. ? set count values in cr20 ? set 16-bit timer mode control register 20 (tmc20) as shown in figure 6-4. figure 6-4. settings of 16-bit timer mode control register 20 for timer interrupt operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 setting of count clock (see table 6-2 ) caution if both the cpt201 and cpt200 flags are set to 0, the capture edge operation is prohibited. when the count value of 16-bit timer counter 20 (tm20) matches the value set in cr20, counting of tm20 continues and an interrupt request signal (inttm20) is generated. table 6-2 shows interval time, and figure 6-5 shows timing of timer interrupt operation. caution when rewriting the value in cr20 during a count operation, be sure to execute the following processing. <1> disable interrupts (set tmmk20 (bit 2 of interrupt mask flag register 1 (mk1)) to 1). <2> disable inversion control of timer output data (set toc20 to 0) if the value in cr20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. table 6-2. interval time of 16-bit timer 20 tcl201 tcl200 count clock interval time 0 0 timer 61 interrupt signal cycle of timer 61 interrupt signal 2 16 011/f x (0.2 s) 2 16 /f x (13.1 ms) 102 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 112 5 /f x (6.4 s) 2 21 /f xt (419 ms) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 114 figure 6-5. timing of timer interrupt operation remark n = 0000h to ffffh count clock tm20 count value cr20 inttm20 to20 tof20 nn n nn interrupt acknowledgement interrupt acknowledgement overflow flag set t 0000h n ffffh n 0000h 0001h 0001h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 115 6.4.2 operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value set to cr20. since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in tcl201 and tcl200. to operate 16-bit timer 20 as a timer output, the following settings are required. ? set p33 to output mode (pm33 = 0). ? reset the output latch of p33 to 0. ? set the count value in cr20. ? set 16-bit timer mode control register 20 (tmc20) as shown in figure 6-6. figure 6-6. settings of 16-bit timer mode control register 20 for timer output operation ? 0/1 0/1 0/1 1 0/1 0/1 1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 setting of count clock (see table 6-2 ) inverse enable of timer output data to20 output enable caution if both the cpt201 flag and cpt200 flag are set to 0, the capture edge operation is prohibited. when the count value of 16-bit timer counter 20 (tm20) matches the value set in cr20, the output status of the to20 pin is inverted. this enables timer output. at that time, tm20 continues counting and an interrupt request signal (inttm20) is generated. figure 6-7 shows the timing of timer output (see table 6-2 for the interval time of 16-bit timer 20). figure 6-7. timer output timing note the initial value of to20 becomes low level when output is enabled (toe20 = 1). remark n = 0000h to ffffh count clock tm20 count value cr20 inttm20 to20 note tof20 nn n nn interrupt acknowledgement interrupt acknowledgement overflow flag set t 0000h n ffffh n 0000h 0001h 0001h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 116 6.4.3 capture operation the capture operation consists of latching the count value of 16-bit timer counter 20 (tm20) into a capture register in synchronization with a capture trigger, and retaining the count value. set tmc20 as shown in figure 6-8 to allow the 16-bit timer to start the capture operation. figure 6-8. settings of 16-bit timer mode control register 20 for capture operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 count clock selection capture edge selection (see table 6-3 ) 16-bit capture register 20 (tcp20) starts a capture operation after a cpt20 capture trigger edge is detected, and latches and retains the count value of 16-bit timer 20. tcp20 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. table 6-3 and figure 6-9 show the settings of the capture edge and the capture operation timing, respectively. table 6-3. settings of capture edge cpt201 cpt200 capture edge selection 0 0 capture operation prohibited 0 1 cpt20 pin rising edge 1 0 cpt20 pin falling edge 1 1 cpt20 pin both edges caution because tcp20 is rewritten when a capture trigger edge is detected during tcp20 read, disable capture trigger edge detection during tcp20 read. figure 6-9. capture operation timing (with both edges of cpt20 pin specified) count clock tm20 count read buffer tcp20 cpt20 0000h 0000h 0001h 0001h undefined n n n m 1 m m m capture start capture start capture edge detection capture edge detection remark n, m = 0000h to ffffh www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 117 6.4.4 16-bit timer counter 20 readout the count value of 16-bit timer counter 20 (tm20) is read out using a 16-bit manipulation instruction. tm20 readout is performed via the counter read buffer. the counter read buffer latches the tm20 count value, the buffer operation is held pending at the cpu clock falling edge after the read signal of the tm20 lower byte rises, and the count value is retained. the retained counter read buffer value can be read out as the count value. cancellation of the pending state is performed at the cpu clock falling edge after the read signal of the tm20 higher byte falls. reset input sets tm20 to 0000h and tm20 starts free running. figure 6-10 shows the timing of 16-bit timer counter 20 readout. cautions 1. the count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. though tm20 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can also be used. when using an 8-bit transfer instruction, execute it by direct addressing. 3. when using an 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. if only the lower byte is read, the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read. figure 6-10. 16-bit timer counter 20 readout timing cpu clock count clock tm20 count read buffer tm20 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period remark n = 0000h to ffffh www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 118 6.5 cautions on using 16-bit timer 20 6.5.1 restrictions when rewriting 16-bit compare register 20 (1) disable interrupts (tmmk20 = 1) and inversion control of timer output (toc20 = 0) before rewriting the compare register (cr20). if the value in cr20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) depending on the timing of rewriting the compare register (cr20), the interval time may become twice as long as the intended time. similarly, a shorter waveform or twice-longer waveform than the intended timer output waveform may be output. to avoid this problem, rewrite the compare register using either of the following procedures. when rewriting using 8-bit access <1> disable interrupts (tmmk20 = 1) and inversion control of timer output (toc20 = 0). <2> first rewrite the higher byte of cr20 (16 bits). <3> then rewrite the lower byte of cr20 (16 bits). <4> clear the interrupt request flag (tmif20). <5> enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from the start of the interrupt. (count clock = 32/f x , cpu clock = f x ) tm20_vct: set1 tmmk20 ; disable timer interrupts (6 clocks) clr1 tmc20.3 ; disable timer output inversion (6 clocks) mov a,#xxh ; set the rewrite value of the higher byte (6 clocks) mov !0ff17h,a ; rewrite the cr20 higher byte (8 clocks) total: 16 clocks or mov a,#yyh ; set the rewrite value of the lower byte (6 clocks) more note mov !0ff16h,a ; rewrite the cr20 lower byte (8 clocks) clr1 tmif20 ; clear the interrupt request flag (6 clocks) clr1 tmmk20 ; enable timer interrupts (6 clocks) set1 tmc20.3 ; enable timer output inversion note because the inttm20 signal becomes high level for half a cycle of the count clock after an interrupt is generated, the output is inverted if toc20 is set to 1 during this period. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 6 16-bit timer 20 user ? s manual u15400ej3v0ud 119 when rewriting using 16-bit access <1> disable interrupts (tmmk20 = 1) and inversion control of timer output (toc20 = 0). <2> rewrite cr20 (16 bits). <3> wait for one cycle or more of the count clock. <4> clear the interrupt request flag (tmif20). <5> enable timer interrupts/timer output inversion. (count clock = 32/f x , cpu clock = f x ) tm20_vct set1 tmmk20 ; disable timer interrupts clr1 tmc20.3 ; disable timer output inversion movw ax,#xxyyh ; set the rewrite value of cr20 movw cr20,ax ; rewrite cr20 nop nop : ; 16 nop instructions (wait for 32/f x ) note nop nop clr1 tmif20 ; clear the interrupt request flag clr1 tmmk20 ; enable timer interrupts set1 tmc20.3 ; enable timer output inversion note clear the interrupt request flag (tmif20) after waiting for one cycle or more of the count clock from the instruction that rewrites cr20 (movw cr20, ax). www.datasheet.co.kr datasheet pdf - http://www..net/
120 user?s manual u15400ej3v0ud chapter 7 8-bit timers 50, 60, and 61 7.1 functions of 8-bit timers 50, 60, and 61 one 8-bit timer channel (timer 50) and two 8-bit timer/event counter channels (timer 60 and 61) are incorporated in the pd789478 subseries. the operation modes listed in the following table can be set via mode register settings. table 7-1. operation modes channel mode timer 50 timer 60 timer 61 8-bit timer counter mode (stand-alone mode) available available available 16-bit timer counter mode (cascade connection mode) available not available carrier generator mode available not available pwm output mode available not available not available ppg output mode not available available available 24-bit event counter mode (connect with 16-bit timer 20) not available not available available (1) mode to use 8-bit timer/event counter as discrete unit (stand-alone mode) the following functions can be used in this mode. ? interval timer with 8-bit resolution ? square wave output with 8-bit resolution ? interval timer with 8-bit resolution ? external event counter with 8-bit resolution ? square wave output with 8-bit resolution (2) mode to use timer 50 and timer 60 connected in cascade (16-bit resolution: cascade connection) operation as a 16-bit timer/event counter is enabled in cascade connection mode. the following functions can be used in this mode. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution (3) carrier generator mode the carrier clock generated by timer 60 is output in the cycle set by timer 50. (4) pwm output mode (pwm: pulse width modulator) pulses are output using any duty ratio (pulse width). the cycle (overflow cycle of the timer) becomes constant (free running). www.datasheet.co.kr datasheet pdf - http://www..net/

user?s manual u15400ej3v0ud 121 (5) ppg output mode (ppg: programmable pulse generator) pulses are output using any cycle or duty ratio (pulse width) set (both the cycle and pulse width are programmable). (6) 24-bit event counter mode operation as an external event counter with 24-bit resolution is enabled using 16-bit timer 20 and timer 61. however, this mode operates only as a counter read function. there is no compare, match, or clear function. <1> select the timer 61 interrupt signal for the count clock of 16-bit timer 20 (tcl201 = 0, tcl200 = 0) <2> set timer 61 in stand-alone mode (tmd611 = 0) select the external clock input from pin tmi61 for the count clock of timer 61 ((tcl612 = 0, tcl611 = 1) or (tcl612 = 1, tcl611 = 0)) <3> set cr61 to ffh <4> read the current count value of 16-bit timer 20 (16-bit timer 20 does not have a count clear function and is counting constantly) <5> enable timer 61 count operation (tce61 = 1) figure 7-1. block diagram of 24-bit event counter internal bus tmi61/to61 /intp2/p32 timer read timer read timer 61 (lower 8 bits) timer 20 (higher 16 bits) select external clock for count clock select timer 61 interrupt signal for count clock www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 122 7.2 configuration of 8-bit timers 50, 60, and 61 8-bit timers 50, 60, and 61 include the following hardware. table 7-2. configuration of 8-bit timers 50, 60, and 61 item configuration timer counter 8 bits 3 (tm50, tm60, tm61) registers compare registers: 8 bits 5 (cr50, cr60, crh60, cr61, crh61) timer outputs 3 (to50, to60, to61) control registers 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 60 (tmc60) carrier generator output control register 60 (tca60) 8-bit timer mode control register 61 (tmc61) port mode register 3 (pm3) port 3 (p3) www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 123 !"##$ %$ teg50 tcl500 tcl501 8-bit timer mode control register 50 (tmc50) decoder selector selector 8-bit compare register 50 (cr50) 8-bit timer counter 50 (tm50) selector count operation start signal (from figure 7-3 (d)) (cascade connection) inttm50 f x /2 3 f x /2 7 timer 60 interrupt request signal (from figure 7-3 (b)) carrier clock (in carrier generator mode) or timer 60 output signal (in other than carrier generator mode) (from figure 7-3 (c)) cascade connection mode match timer 60 match signal (from figure 7-3 (e)) (in cascade connection mode) internal bus ovf bit 7 of tm60 (from figure 7-3 (a)) toe50 p30 output latch pm30 timer 50 match signal (to figure 7-3 (f)) (in cascade connection mode) timer 50 match signal (to figure 7-3 (g)) (in carrier generator mode) to50/tmi60/ intp0/p30 tce50 tcl502 f x f xt tmd500 tmd501 s q in r q ck clear pwm mode www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 124 & !"##$ %$ tce60 tcl602 tcl601 tcl600 tmd601 tmd600 toe600 8-bit timer mode control register 60 (tmc60) carrier generator output control register 60 (tca60) decoder 8-bit timer counter 60 (tm60) f/f tm50 match signal (in cascade connection mode) count operation start signal to timer 50 (in cascade connection mode) timer counter match signal for tm60 (in cascade connection mode) clear 8-bit compare register 60 (cr60) selector output controller note to figure 7-2 (d) count clock signal input to tm50 inttm60 bit 7 of tm60 (in cascade connection mode) (to figure 7-2 (a)) timer counter match signal (from timer 50 in figure 7-2 (g)) (in carrier generator mode) from figure 7-2 (f) to figure 7-2 (e) match to60/intp1/p31 carrier clock (in carrier generator mode) or timer 60 output signal (in other than carrier generator mode) (to figure 7-2 (c)) reset ppg mode cascade connection mode 8-bit h width compare register 60 (crh60) internal bus selector ovf timer 60 interrupt request signal (to figure 7-2 (b)) f x f x /2 2 tmi60/to50/ intp0/p30 f tmi /2 f tmi /2 2 f tmi /2 3 prescaler f tmi rmc60 nrzb60 nrz60 '
www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 125 ( !"##$ %$ tce61 tcl612 tcl611 tcl610 tmd611 tmd610 toe610 8-bit timer mode control register 61 (tmc61) decoder 8-bit timer counter 61 (tm61) f/f clear 8-bit compare register 61 (cr61) selector inttm61 match to61/tmi61 /intp2/p32 reset ppg mode 8-bit h width compare register 61 (crh61) internal bus selector timer 61 interrupt request signal (in 24-bit event counter mode) to timer 20 count clock input signal in figure 6-1 f x f x /2 4 tmi61/to61 /intp2/p32 f tmi /2 f tmi /2 2 f tmi /2 3 f tmi prescaler p32 output latch pm32 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 126 figure 7-5. block diagram of output controller (timer 60) f/f rmc60 nrz60 toe60 pm31 p31 output latch selector to60/intp1/p31 carrier generator mode carrier clock (in carrier generator mode) or timer 60 output signal (in other than carrier generator mode) (1) 8-bit compare register 50 (cr50) this 8-bit register is used to continually compare the value set to cr50 with the count value in 8-bit timer counter 50 (tm50) and to issue an interrupt request (inttm50) when a match occurs. in pwm mode, this register is used for high-level width setting. cr50 is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. cautions 1. in pwm output mode (tmd501 = 1, tmd500 = 0), if cr50 is rewritten while the timer is operating, a high level may be output for one clock cycle immediately after this rewrite operation. if this waveform may cause problems in the application, either <1> stop the timer when rewriting cr50, or <2> rewrite cr50 after toe50 has been cleared. 2. if both edges have been selected as the valid edge of the count clock in pwm output mode (teg50 = 1), do not set cr50 to 00h, 01h, or ffh. also, if the rising edge has been selected as the valid edge (teg50 = 0), do not set cr50 to 00h. (2) 8-bit compare register 60 (cr60) this 8-bit register is used to continually compare the value set to cr60 with the count value in 8-bit timer counter 60 (tm60) and to issue an interrupt request (inttm60) when a match occurs. in carrier generator mode and ppg mode, this register is used for low-level width setting. when connected to tm50 via a cascade connection and using as a 16-bit timer/event counter, the interrupt request (inttm60) occurs only when matches occur simultaneously between cr50 and tm50 and between cr60 and tm60 (inttm50 is not generated). cr60 is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. (3) 8-bit h width compare registers 60 and 61 (crh60, crh61) in ppg output mode, the high-level width of timer output is set by writing a value to crh6n. crh6n is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. remark n = 0, 1 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 127 (4) 8-bit compare register 61 (cr61) this 8-bit register is used to continually compare the value set to cr61 with the count value in 8-bit timer counter 61 (tm61) and issue an interrupt request (inttm61) when a match occurs. in ppg mode, this registered used for low-level width setting. cr61 is set with an 8-bit memory manipulation instruction. reset input makes this register undefined. (5) 8-bit timer counters 50, 60, and 61(tm50, tm60, tm61) these are 8-bit registers that are used to count the count pulse. tm50, tm60, and tm61 are read with an 8-bit memory manipulation instruction. reset input sets these register values to 00h. tm50, tm60, and tm61 are cleared to 00h under the following conditions. (a) stand-alone mode ? after reset ? when tcemn (bit 7 of 8-bit timer mode control register mn (tmcmn)) is cleared to 0 ? when a match occurs between tmmn and crmn ? when the tmmn count value overflows remark mn = 50, 60, 61 (b) cascade connection mode (tm50 and tm60 are simultaneously cleared to 00h) ? after reset ? when the tce60 flag is cleared to 0 ? when matches occur simultaneously between tm50 and cr50 and between tm60 and cr60 ? when the tm50 and tm60 count values overflow simultaneously (c) carrier generator (tm60) and ppg output mode (tm60 and tm61) ? after reset ? when the tce6n flag is cleared to 0 ? when a match occurs between tm6n and cr6n ? when a match occurs between tm6n and crh6n ? when the tm6n count value overflows remark n = 0, 1 (d) pwm output mode (tm50) ? after reset ? when the tce50 flag is cleared to 0 ? when the tm50 count value overflows www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 128 7.3 control registers for 8-bit timers 50, 60, and 61 8-bit timers 50, 60, and 61 are controlled by the following six registers. ? 8-bit timer mode control register 50 (tmc50) ? 8-bit timer mode control register 60 (tmc60) ? carrier generator output control register 60 (tca60) ? 8-bit timer mode control register 61 (tmc61) ? port mode register 3 (pm3) ? port 3 (p3) (1) 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 50 (tmc50) is used to control the timer 50 count clock setting and the operation mode setting. tmc50 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 7-6. format of 8-bit timer mode control register 50 (1/2) symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc50 tce50 teg50 tcl502 tcl501 tcl500 tmd501 tmd500 toe50 ff4dh 00h r/w tce50 control of tm50 count operation ' 0 clear tm50 count value and stop operation 1 start count operation teg50 selection of valid edge of tm50 count clock 0 count at the rising edge of the count clock 1 count at both edges of the count clock ' tcl502 tcl501 tcl500 selection of timer 50 count clock 000f (5.0 mhz) 001f /2 (625 khz) 010f /2 (39.1 khz) 011f (32.768 khz) 1 0 0 timer 60 match signal (inttm60) 1 0 1 carrier clock (in carrier generator mode) or timer 60 output signal (in other than carrier generator mode) other than above setting prohibited tmd501 tmd500 tmd601 tmd600 selection of operation mode for timer 50 '& 00 0 stand-alone mode (8-bit counter mode) 0 1 0 1 16-bit counter mode (cascade connection mode) 0 0 1 1 carrier generator mode 10 0 pwm output mode other than above setting prohibited www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 129 figure 7-6. format of 8-bit timer mode control register 50 (2/2) symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc50 tce50 teg50 tcl502 tcl501 tcl500 tmd501 tmd500 toe50 ff4dh 00h r/w toe50 control of timer output '( 0 output disabled 1 output enabled notes 1. since the count operation is controlled by tce60 (bit 7 of tmc60) in cascade connection mode, any setting for tce50 is ignored. 2. selection of both edges is valid only in pwm mode. in 8-bit counter mode or cascade connection mode, even if teg50 is set to 1, counting occurs at the rising edge. 3. the operation mode selection is set by a combination of the tmc50 and tmc60 registers. 4. since timer 50 output is disabled in cascade connection mode, set toe50 to 0. cautions 1. in cascade connection mode, the timer 60 output signal is forcibly selected for the count clock. 2. to manipulate tmc50, follow the setting procedure below. <1> set the tm50 count operation to stop. <2> set the operation mode and count clock. <3> the count operation starts. remarks 1. f : main system clock oscillation frequency 2. f : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f = 5.0 mhz or f = 32.768 khz. 4. : don ? t care (2) 8-bit timer mode control register 60 (tmc60) 8-bit timer mode control register 60 (tmc60) is used to control the timer 60 count clock setting and the operation mode setting. tmc60 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 130 figure 7-7. format of 8-bit timer mode control register 60 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc60 tce60 0 tcl602 tcl601 tcl600 tmd601 tmd600 toe600 ff4eh 00h r/w tce60 control of tm60 count operation ' 0 clear tm60 count value and stops operation (the count value is also cleared for tm50 in cascade connection mode) 1 start count operation (the count operation is also started for tm50 in cascade connection mode) tcl602 tcl601 tcl600 selection of timer 60 count clock 000f (5.0 mhz) 001 f /2 (1.25 mhz) 010f 011f /2 100 f /2 101 f /2 other than above setting prohibited tmd501 tmd500 tmd601 tmd600 selection of operation mode for timer 60 ' 0 0 0 stand-alone mode (8-bit counter mode) 0 1 0 1 16-bit counter mode (cascade connection mode) 0 0 1 1 carrier generator mode 0 1 0 ppg output mode other than above setting prohibited toe600 control of timer output 0 output disabled 1 output enabled notes 1. since the count operation is controlled by tce60 (bit 7 of tmc60) in cascade connection mode, any setting for tce50 is ignored. 2. the operation mode selection is set by a combination of the tmc50 and tmc60 registers. caution to manipulate tmc60, follow the setting procedure below. <1> set the tm60 count operation to stop. <2> set the operation mode and count clock. <3> the count operation starts. remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. 4. : don ? t care www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 131 (3) carrier generator output control register 60 (tca60) this register is used to set the timer output data in carrier generator mode. tca60 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 7-8. format of carrier generator output control register 60 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w tca60 0 0 0 0 0 rmc60 nrzb60 nrz60 ff4fh 00h r/w ' rmc60 control of remote control output 0 when nrz60 = 1, a carrier pulse is output to to60/intp1/p31 pin (when nrz60 = 0, a low level is output to to60/intp1/p31 pin) 1 when nrz60 = 1, high-level signal is output to to60/intp1/p31 pin (when nrz60 = 0, a low level is output to to60/intp1/p31 pin) nrzb60 this is the bit that stores the next data to be output to nrz60. when a match signal occurs (for a match with timer 50), the data is output to nrz60. nrz60 no return zero data 0 output low-level signal (carrier clock is stopped) 1 output carrier pulse or high-level signal note bit 0 is write-only cautions 1. at the count start, input the values of the data reloaded from nrzb60 to nrz60. for nrzb60, input the data required by the program in advance. 2. when timer 60 output is disabled (toe600 = 0), use of a 1-bit memory manipulation instruction for tca60 output is disabled (only an 8-bit memory manipulation instruction can be used). 3. when timer 60 output is enabled (toe600 = 1), a write operation to nrz is invalid. however, while the timer 50 interrupt signal (inttm50) is high level, the nrzb60 value is immediately transferred to nrz60 if tca60 is rewritten. rewrite tca60 after waiting for half a clock of the tm50 count clock during inttm50 interrupt servicing. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 132 (4) 8-bit timer mode control register 61 (tmc61) 8-bit timer mode control register 61 (tmc61) is used to control the timer 61 count clock setting and the operation mode setting. tmc61 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 7-9. format of 8-bit timer mode control register 61 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc61 tce61 0 tcl612 tcl611 tcl610 tmd611 tmd610 toe610 ff41h 00h r/w tce61 control of tm61 count operation 0 clear tm61 count value and stop operation 1 start count operation tcl612 tcl611 tcl610 selection of timer 61 count clock ' 00 0f (5.0 mhz) 00 1 f /2 (313 khz) 01 0f 01 1f /2 10 0f /2 10 1f /2 other than above setting prohibited tmd611 tmd610 selection of operation mode for timer 61 ' 0 0 stand-alone mode (8-bit counter mode) 1 0 ppg output mode other than above setting prohibited toe610 control of timer output 0 output disabled 1 output enabled note to set the register in 24-bit event counter mode, the external input clock and stand-alone mode need to be selected. caution to manipulate tmc61, follow the setting procedure below. <1> set the tm61 count operation to stop. <2> set the operation mode and count clock. <3> the count operation starts. remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 133 (5) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. when using the p30/intp0/to50/tmi60 pin as a timer output (to50), set pm30 and the p30 output latch to 0. when used as a timer input (tmi60), set pm30 to 1. when using the p31/intp1/to60 pin as a timer output (to60), set pm31 and the p31 output latch to 0. when using the p32/intp2/to61/tmi61 pin as a timer input (tmi61), set pm32 to 1. when used as a timer output (to61), set pm32 and the p32 output latch to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 7-10. format of port mode register 3 symbol76543210addressafter resetr/w pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 ff23h ffh r/w pm3n i/o mode of p3n pin (n = 0 to 2) 0 output mode (output buffer is on) 1 input mode (output buffer is off) www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 134 7.4 operation of 8-bit timers 50, 60, and 61 7.4.1 operation as 8-bit timer counter timer 50, timer 60, and timer 61 can be independently used as 8-bit timer counters. the following modes can be used for the 8-bit timer counter. ? interval timer with 8-bit resolution ? external event counter with 8-bit resolution (timer 60 and timer 61 only) ? square wave output with 8-bit resolution (1) operation as interval timer with 8-bit resolution the interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register nm (crnm). to operate 8-bit timer nm as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter nm (tmnm) (tcenm = 0). <2> for timer 50, disable timer output of to50 (toe50 = 0). for timer 60, disable timer output of to60 (toe600 = 0). for timer 61, disable timer output of to61 (toe610 = 0). <3> set a count value in crnm. <4> set the operation mode of timer nm to 8-bit timer counter mode (see figures 7-6, 7-7, and 7-9). <5> set the count clock for timer nm (see figures 7-6, 7-7, and 7-9). <6> enable the operation of tmnm (tcenm = 1). when the count value of 8-bit timer counter nm (tmnm) matches the value set in crnm, tmnm is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmnm) is generated. tables 7-3 to 7-5 show the interval time, and figures 7-11 to 7-16 show the timing of the interval timer operation. caution be sure to stop the timer operation before overwriting the count clock with different data. remark nm = 50, 60, 61 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 135 table 7-3. interval time of timer 50 tcl502 tcl501 tcl500 minimum interval time maximum interval time resolution 0001/f (0.2 s) 2 /f (51.2 s) 1/f (0.2 s) 0012 /f (1.6 s) 2 /f (409.6 s) 2 /f (1.6 s) 0102 /f (25.6 s) 2 /f (6.55 ms) 2 /f (25.6 s) 0111/f (30.5 s) 2 /f (7.81 ms) 1/f (30.5 s) 1 0 0 input cycle of timer 60 match signal input cycle of timer 60 match signal 2 input cycle of timer 60 match signal 1 0 1 input cycle of timer 60 output i nput cycle of timer 60 output 2 input cycle of timer 60 remarks 1. f : main system clock oscillation frequency 2. f : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f = 5.0 mhz or f = 32.768 khz. table 7-4. interval time of timer 60 tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0001/f (0.2 s) 2 /f (51.2 s) 1/f (0.2 s) 0012 /f (0.8 s) 2 /f (204 s) 2 /f (0.8 s) 010f input cycle f input cycle 2 f input cycle 011f /2 input cycle f /2 input cycle 2 f /2 input cycle 100f /2 input cycle f /2 input cycle 2 f /2 input cycle 101f /2 input cycle f /2 input cycle 2 f /2 input cycle remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. table 7-5. interval time of timer 61 tcl612 tcl611 tcl610 minimum interval time maximum interval time resolution 0001/f (0.2 s) 2 /f (51.2 s) 1/f (0.2 s) 0012 /f (3.2 s) 2 /f (819 s) 2 /f (3.2 s) 010f input cycle f input cycle 2 f input cycle 011f /2 input cycle f /2 input cycle 2 f /2 input cycle 100f /2 input cycle f /2 input cycle 2 f /2 input cycle 101f /2 input cycle f /2 input cycle 2 f /2 input cycle remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 136 figure 7-11. timing of interval timer operation with 8-bit resolution (basic operation) count stop count clock crnm tcenm inttmnm tonm n t tmnm n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement interval time interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. nm = 50, 60, 61 figure 7-12. timing of interval timer operation with 8-bit resolution (when crnm is set to 00h) count clock crnm tcenm inttmnm tonm 00h tmnm 00h count start remark nm = 50, 60, 61 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 137 figure 7-13. timing of interval timer operation with 8-bit resolution (when crnm is set to ffh) count clock crnm tcenm inttmnm tonm ffh tmnm ffh 00h 01h 00h 01h 00h 01h 00h 01h ffh ffh ffh clear clear clear count start remark nm = 50, 60, 61 figure 7-14. timing of interval timer operation with 8-bit resolution (when crnm changes from n to m (n < < < < m)) count clock crnm tcenm inttmnm tonm tmnm n 00h 00h n 00h 01h 00h 01h m nm n m clear clear clear count start interrupt acknowledgement interrupt acknowledgement crnm overwritten remark 00h n < m ffh nm = 50, 60, 61 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 138 figure 7-15. timing of interval timer operation with 8-bit resolution (when crnm changes from n to m (n > > > > m)) count clock crnm tcenm inttmnm tonm tmnm 00h 00h 00h n ? 1 n mn m n m 00h ffh m h clear clear clear tmnm overflows because m < n crnm overwritten remark 00h m < n ffh nm = 50, 60, 61 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 139 figure 7-16. timing of interval timer operation with 8-bit resolution (when timer 60 match signal is selected for timer 50 count clock) timer 60 count clock cr60 tce60 inttm60 to60 tm60 n 00h m 00h 00h 01h m n m 00h m 00h 00h 01h y ? 1 y 00h y 00h y input clock to timer 50 (timer 60 match signal) to50 inttm50 tce50 cr50 tm50 clear clear clear clear count start count start remark 00h n < m ffh y = 00h to ffh www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 140 (2) operation as external event counter with 8-bit resolution (timer 60 and timer 61 only) the external event counter counts the number of external clock pulses input to the tmi6m pin by using 8-bit timer counter 6m (tm6m). to operate timer 6m as an external event counter, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 6m (tm6m) (tce6m = 0). <2> disable timer output of to6m (toe6m0 = 0). <3> when using timer 60, set p30 to input mode (pm30 = 1). when using timer 61, set p32 to input mode (pm32 = 1). <4> select the external input clock for timer 6m (see figures 7-7 and 7-9). <5> set the operation mode of timer 6m to 8-bit timer counter mode (see figures 7-7 and 7-9). <6> set a count value in cr6m. <7> enable the operation of tm6m (tce6m = 1). each time the valid edge is input, the value of tm6m is incremented. when the count value of tm6m matches the value set in cr6m, tm6m is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttm6m) is generated. figure 7-17 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count clock with different data. remark m = 0, 1 figure 7-17. timing of operation of external event counter with 8-bit resolution tmi6m pin input tm6m count value cr6m tce6m inttm6m 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remark n = 00h to ffh www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 141 (3) operation as square-wave output with 8-bit resolution square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register nm (crnm). to operate timer nm for square-wave output, settings must be made in the following sequence. <1> when using timer 50, set p30 to output mode (pm30 = 0) and the p30 output latch to 0, respectively. when using timer 60, set p31 to output mode (pm31 = 0) and the p31 output latch to 0, respectively. when using timer 61, set p32 to output mode (pm32 = 0) and the p32 output latch to 0, respectively. <2> disable operation of timer counter nm (tmnm) (tcenm = 0). <3> set a count clock for timer nm (see figures 7-6, 7-7 and 7-9) <4> for timer 50, enable timer output of to50 (toe50 = 0). for timer 60, disable timer output of to60 (toe600 = 0). for timer 61, disable timer output of to61 (toe610 = 0). <5> set a count value in crnm. <6> enable the operation of tmnm (tcenm0 = 1). when the count value of tmnm matches the value set in crnm, the tonm pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tmnm is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmnm) is generated. the square-wave output is cleared to 0 by setting tcenm to 0. tables 7-6 to 7-8 show the square-wave output range, and figure 7-18 shows the timing of square-wave output. caution be sure to stop the timer operation before overwriting the count clock with different data. remark nm = 50, 60, 61 table 7-6. square-wave output range of timer 50 tcl502 tcl501 tcl500 minimum pulse width maximum pulse width resolution 0001/f (0.2 s) 2 /f (51.2 s) 1/f (0.2 s) 0012 /f (1.6 s) 2 /f (409.6 s) 2 /f (1.6 s) 0102 /f (25.6 s) 2 /f (6.55 ms) 2 /f (25.6 s) 0111/f (30.5 s) 2 /f (7.81 ms) 1/f (30.5 s) 1 0 0 input cycle of timer 60 match signal input cycle of timer 60 match signal 2 input cycle of timer 60 match signal 1 0 1 input cycle of timer 60 output i nput cycle of timer 60 output 2 input cycle of timer 60 remarks 1. f : main system clock oscillation frequency 2. f : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f = 5.0 mhz or f = 32.768 khz. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 142 table 7-7. square-wave output range of timer 60 tcl602 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0001/f (0.2 s) 2 /f (51.2 s) 1/f (0.2 s) 0012 /f (0.8 s) 2 /f (204 s) 2 /f (0.8 s) 010f input cycle f input cycle 2 f input cycle 011f /2 input cycle f /2 input cycle 2 f /2 input cycle 100f /2 input cycle f /2 input cycle 2 f /2 input cycle 101f /2 input cycle f /2 input cycle 2 f /2 input cycle remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. table 7-8. square-wave output range of timer 61 tcl612 tcl611 tcl610 minimum pulse width maximum pulse width resolution 0001/f (0.2 s) 2 /f (51.2 s) 1/f (0.2 s) 0012 /f (3.2 s) 2 /f (819 s) 2 /f (3.2 s) 010f input cycle f input cycle 2 f input cycle 011f /2 input cycle f /2 input cycle 2 f /2 input cycle 100f /2 input cycle f /2 input cycle 2 f /2 input cycle 101f /2 input cycle f /2 input cycle 2 f /2 input cycle remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. figure 7-18. timing of square-wave output with 8-bit resolution count clock crnm tcenm inttmnm tonm note n tmnm n 00h 01h n 00h 01h n 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement note the initial value of tonm is low level when output is enabled. remark n = 00h to ffh nm = 50, 60, 61 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 143 7.4.2 operation as 16-bit timer counter timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. in this case, 8-bit timer counter 50 (tm50) is the higher 8 bits and 8-bit timer counter 60 (tm60) is the lower 8 bits. 8-bit timer 60 controls reset and clear. the following modes can be used for the 16-bit timer counter. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution (1) operation as interval timer with 16-bit resolution the interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 50 (cr50) and 8-bit compare register 60 (cr60). to operate as an interval timer with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 50 (tm50) and 8-bit timer counter 60 (tm60) (tce50 = 0, tce60 = 0). <2> disable timer output of to60 (toe600 = 0). <3> set the count clock for timer 60 (see figure 7-7). <4> set the operation mode of timer 50 and timer 60 to 16-bit timer counter mode (see figures 7-6 and 7-7). <5> set a count value in cr50 and cr60. <6> enable the operation of tm50 and tm60 (tce60 = 1 ' ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). when the count values of tm50 and tm60 match the values set in cr50 and cr60 respectively, both tm50 and tm60 are simultaneously cleared to 00h and continues counting. at the same time, an interrupt request signal (inttm60) is generated (inttm50 is not generated). table 7-9 shows interval time, and figure 7-19 shows the timing of the interval timer operation. cautions 1. be sure to stop the timer operation before overwriting the count clock with different data. 2. in the 16-bit timer counter mode, to50 cannot be used. be sure to set toe50 = 0 to disable to50 output. table 7-9. interval time with 16-bit resolution tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0001/f (0.2 s) 2 /f (13.1 ms) 1/f (0.2 s) 0012 /f (0.8 s) 2 /f (52.4 ms) 2 /f (0.8 s) 010f input cycle f input cycle 2 f input cycle 011f /2 input cycle f /2 input cycle 2 f /2 input cycle 100f /2 input cycle f /2 input cycle 2 f /2 input cycle 101f /2 input cycle f /2 input cycle 2 f /2 input cycle remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 144 )$* % *'+#$,-#' *.'/'0 ' * interval time count clock tm60 count value cr60 tce60 inttm60 to60 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x ? 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h t not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement $#"
+ + ! "## ## www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 145 (2) operation as external event counter with 16-bit resolution the external event counter counts the number of external clock pulses input to the tmi60 pin by tm50 and tm60. to operate as an external event counter with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable timer output of to60 (toe600 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clock for timer 60 (see figure 7-7). <5> set the operation mode of timer 50 and timer 60 to 16-bit timer counter mode (see figures 7-6 and 7-7). <6> set a count value in cr50 and cr60. <7> enable the operation of tm50 and tm60 (tce60 = 1 ' ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). each time the valid edge is input, the values of tm50 and tm60 are incremented. when the count values of tm50 and tm60 simultaneously match the values set in cr50 and cr60 respectively, both tm50 and tm60 are cleared to 00h and continues counting. at the same time, an interrupt request signal (inttm60) is generated (inttm50 is not generated). figure 7-20 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count clock with different data. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 146 $* %1'*#+*' *',-#' *.'/'0 ' * tmi60 pin input tm60 count value cr60 tce60 inttm60 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h x ? 1 not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement $#" ## ## www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 147 (3) operation as square-wave output with 16-bit resolution square waves of any frequency can be output at an interval specified by the count value preset in cr50 and cr60. to operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable output of to50 and to60 (toe50 = 0, toe600 = 0). <3> set a count clock for timer 60. (see figure 7-7) <4> set p31 to the output mode (pm31 = 0), set the p31 output latch to 0, and set to60 to output enable (toe600 = 1). (use of to50 is prohibited.) <5> set the operation mode of timer 50 and timer 60 to 16-bit timer counter mode (see figures 7-6 and 7-7). <6> set count values in cr50 and cr60. <7> enable the operation of tm60 (tce60 = 1 ' ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). when the count values of tm50 and tm60 simultaneously match the values set in cr50 and cr60 respectively, the to60 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tm50 and tm60 are cleared to 00h and continue counting. at the same time, an interrupt request signal (inttm60) is generated (inttm50 is not generated). the square-wave output is cleared to 0 by setting tce60 to 0. table 7-10 shows the square-wave output range, and figure 7-21 shows timing of square-wave output. cautions 1. be sure to stop the timer operation before overwriting the count clock with different data. 2. in the 16-bit timer counter mode, to50 cannot be used. be sure to set toe50 = 0 to disable to50 output. table 7-10. square-wave output range with 16-bit resolution tcl602 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0001/f (0.2 s) 2 /f (13.1 ms) 1/f (0.2 s) 0012 /f (0.8 s) 2 /f (52.4 ms) 2 /f (0.8 s) 010f input cycle f input cycle 2 f input cycle 011f /2 input cycle f /2 input cycle 2 f /2 input cycle 100f /2 input cycle f /2 input cycle 2 f /2 input cycle 101f /2 input cycle f /2 input cycle 2 f /2 input cycle remarks 1. f : main system clock oscillation frequency 2. f : external input clock frequency 3. the parenthesized values apply to operation at f = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 148 $* %2#3#+,'-'.'/'0 ' * count clock tm60 count value cr60 tce60 inttm60 to60 note ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x ? 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement ' $

%&'
(

($%)% *
$#" ## ## www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 149 7.4.3 operation as carrier generator an arbitrary carrier clock generated by tm60 can be output in the cycle set in tm50. to operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable timer output of to50 and to60 (toe50 = 0, toe600 = 0). <3> set count values in cr50, cr60, and crh60. <4> set the operation mode of timer 50 and timer 60 to carrier generator mode (see figures 7-6 and 7-7). <5> set the count clock for timer 50 and timer 60. <6> set remote control output to carrier pulse (rmc60 (bit 2 of carrier generator output control register 60 (tca60)) = 0). input the required value to nrzb60 (bit 1 of tca60) by program. input a value to nrz60 (bit 0 of tca60) before it is reloaded from nrzb60. <7> set p31 to the output mode (pm31 = 0), set the p31 output latch to 0, and set to60 to output enable (toe600 = 1). <8> enable the operation of tm50 and tm60 (tce50 = 1, tce60 = 1). the operation of the carrier generator is as follows. <1> when the count value of tm60 matches the value set in cr60, an interrupt request signal (inttm60) is generated and output of timer 60 is inverted, which makes the compare register switch from cr60 to crh60. <2> after that, when the count value of tm60 matches the value set in crh60, an interrupt request signal (inttm60) is generated and output of timer 60 is inverted again, which makes the compare register switch from crh60 to cr60. <3> the carrier clock is generated by repeating <1> and <2> above. <4> when the count value of tm50 matches the value set in cr50, an interrupt request signal (inttm50) is generated. the rising edge of inttm50 is the data reload signal of nrzb60 and is transferred to nrz60. <5> when nrz60 is 1, a carrier clock is output from the to60 pin. cautions 1. while timer 60 output is disabled (toe600 = 0), tca60 cannot be set with a 1-bit memory manipulation instruction. be sure to use an 8-bit memory manipulation instruction. 2. when setting the carrier generator operation again after stopping it once, reset nrzb60 because the previous value is not retained. in this case also a 1-bit memory manipulation instruction cannot be used while timer 60 output is disabled (toe600 = 0). be sure to use an 8-bit memory manipulation instruction. 3. when timer 60 output is enabled (toe600 = 1), a write operation to nrz is invalid. however, while the timer 50 interrupt signal (inttm50) is high level, the nrzb60 value is immediately transferred to nrz60 if tca60 is rewritten. rewrite tca60 after waiting for half a clock of the tm50 count clock during inttm50 interrupt servicing. figures 7-22 to 7-24 show the operation timing of the carrier generator. www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 150 figure 7-22. timing of carrier generator operation (when cr60 = n, crh60 = m (m > > > > n)) count clock tm60 count value cr60 tce60 inttm60 m 00h n 00h 01h n crh60 m n 00h carrier clock n 00h 00h n m 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 carrier clock clear clear clear clear count start remark 00h n < m ffh, l = 00h to ffh www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 151 figure 7-23. timing of carrier generator operation (when cr60 = n, crh60 = m (m < < < < n)) count clock tm60 count value cr60 tce60 inttm60 n 00h n crh60 m carrier clock n 00h 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 carrier clock m 00h m m 00h m 00h clear clear clear clear count start l remark 00h m < n ffh, l = 00h to ffh www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 152 figure 7-24. timing of carrier generator operation (when cr60 = crh60 = n) count clock tm60 count value cr60 tce60 inttm60 n 00h 00h 00h n crh60 n n carrier clock 00h 00h n n 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 carrier clock n n 00h clear clear clear clear clear count start l remark n = 00h to ffh, l = 00h to ffh www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 153 7.4.4 pwm free-running mode operation (timer 50) in the pwm free-running mode, to50 becomes high level when tm50 overflows, and to50 becomes low level when cr50 and tm50 match. it is thus possible to output a pulse with any duty ratio. to operate timer 50 in the pwm free-running mode, settings must be made in the following sequence. <1> disable operation of tm50 (tce50 = 0). <2> disable timer output of to50 (toe50 = 0). <3> set a count value to cr50. <4> set the operation mode of timer 50 to the pwm free-running mode (see figure 7-6). <5> set the count clock for timer 50. <6> set p30 to the output mode (pm30 = 0) and the p30 output latch to 0 and enable timer output of to50 (toe50 = 1). <7> enable the operation of tm50 (tce50 = 1). the operation in the pwm free-running mode is as follows. <1> when the count value of tm50 matches the value set in cr50, an interrupt request signal (inttm50) is generated and a low level is output by the to50. the tm50 continues counting without being cleared. <2> to50 outputs a high level when the tm50 overflows. a pulse of any duty is output by repeating the above procedure. figures 7-25 to 7-28 show the operation timing in the pwm free-running mode. figure 7-25. operation timing in pwm free-running mode (when rising edge is selected) caution when the rising edge is selected, do not set cr50 to 00h. if cr50 is set to 00h, pwm output may not be performed normally. remark n = 00h to ffh count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh n ffh n overflow count start overflow overflow www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 154 figure 7-26. operation timing when overwriting cr50 (when rising edge is selected) (1) when setting cr50 > > > > tm50 after overflow (2) when setting cr50 < < < < tm50 after overflow count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh ffh 01h 01h 02h 01h overflow overflow overflow count start cr50 overwrite overflow occurs but no change takes place because to50 is high level. remark n, m = 00h to ffh count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh m ffh 01h m overflow overflow overflow count start cr50 overwrite www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 155 figure 7-27. operation timing in pwm free-running mode (when both edges are selected) (1) cr50 = even number (2) when cr50 = odd number count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n + 1 00h 00h 01h ffh ffh 2n + 1 01h 01h 00h overflow overflow overflow count start caution when both edges are selected, do not set cr50 to 00h, 01h, and ffh. if cr50 is set to these values, pwm output may not be performed normally. remark n = 00h to ffh count clock cr50 tce50 inttm50 to50 2n tm50 2n 00h 00h 01h ffh ffh 2n 02h feh 01h 02h feh overflow count start overflow www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 156 figure 7-28. operation timing in pwm free-running mode (when both edges are selected) (when cr50 is overwritten) remark n = 00h to ffh count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n 00h 00h 00h 01h ffh ffh 01h 2n + 1 01h 02h feh 2n overflow overflow overflow count start cr50 overwrite www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 157 7.4.5 operation as pwm pulse generator (timer 60 and timer 61) in the pwm pulse generator mode, a pulse of any duty ratio can be output by setting a low-level width using cr6m and a high-level width using crh6m. to operate timer 6m in pwm pulse generator mode, settings must be made in the following sequence. <1> disable operation of tm6m (tce6m = 0). <2> disable timer output of to6m (toe6m0 = 0). <3> set count values in cr6m and crh6m. <4> set the operation mode of timer 6m to the pwm pulse generator mode (see figures 7-7 and 7-9). <5> set the count clock for timer 6m. <6> set p32 to the output mode (pm32 = 0) and the p32 output latch to 0 and enable timer output of to6m (toe6m0 = 1). <7> enable the operation of tm6m (tce6m = 1). the operation in the pwm output mode is as follows. <1> when the count value of tm6m matches the value set in cr6m, an interrupt request signal (inttm6m) is generated and output of timer 6m is inverted, which makes the compare register switch from cr6m to crh6m. <2> a match between tm6m and cr6m clears the tm6m value to 00h and then counting starts again. <3> after that, when the count value of tm6m matches the value set in crh6m, an interrupt request signal (inttm6m) is generated and output of timer 6m is inverted again, which makes the compare register switch from crh6m to cr6m. <4> a match between tm6m and crh6m clears the tm6m value to 00h and then counting starts again. a pulse of any duty ratio is output by repeating <1> to <4> above. figures 7-29 and 7-30 show the operation timing in the pwm pulse generator mode. remark m = 0, 1 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 158 figure 7-29. pwm pulse generator mode timing (basic operation) count clock tm6m count value cr6m tce6m inttm6m 00h n 00h 01h n crh6m m n to6m note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of to6m is low level when output is enabled (toe6m0 = 1). remark n, m = 00h to ffh m = 0, 1 www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 159 figure 7-30. pwm pulse generator mode timing (when cr6m and crh6m are overwritten) note the initial value of to6m is low level when output is enabled (toe6m0 = 1). remark n, m, x, y = 00h to ffh m = 0, 1 count clock tm6m count value cr6m tce6m inttm6m 00h n 00h 01h n crh6m m n to6m note m x y 00h 00h x 00h x ym clear clear clear clear count start www.datasheet.co.kr datasheet pdf - http://www..net/

user ? s manual u15400ej3v0ud 160 7.5 cautions on using 8-bit timers 50, 60, and 61 (1) error on starting timer an error of up to 1 clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counter nm (tmnm) is started asynchronously to the count pulse. figure 7-31. start timing of 8-bit timer counter count pulse tmnm count value 00h 01h 02h 03h 04h timer start remark nm = 50, 60, 61 (2) setting of 8-bit compare register nm 8-bit compare register nm (crnm) can be set to 00h. therefore, one pulse can be counted when the 8-bit timer operates as an event counter. remark nm= 50, 60, 61 figure 7-32. timing of operation as external event counter (8-bit resolution) tmi60 input cr60 00h tm60 count value 00h 00h 00h 00h interrupt request flag www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 161 chapter 8 watch timer 8.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch and interval timers can be used at the same time. figure 8-1 shows a block diagram of the watch timer. figure 8-1. block diagram of watch timer f x /2 7 f xt /2 f xt selector selector f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wts wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) watch timer interrupt time selection register (wtim) internal bus 1/2 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 8 watch timer user ? s manual u15400ej3v0ud 162 (1) watch timer an interrupt request (intwt) occurs at an interval of 0.5 second when using either the 4.19 mhz main system clock or the 32.768 khz subsystem clock. also, an interrupt request (intwt) occurs at an interval of 1.0 seconds when using the 32.768 khz subsystem clock via a setting in the watch timer interrupt time selection register (wtim). caution an interval of 0.5 second cannot be created when using the 5.0 mhz main system clock. instead, switch to the 32.768 khz subsystem clock, and then create the 0.5-second interval. (2) interval timer an interrupt request (intwti) occurs at preset intervals. table 8-1. interval time of interval timer interval time at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz at f xt /2 = 16.384 khz 2 4 1/f w 409.6 s 488 s 488 s 976 s 2 5 1/f w 819.2 s 977 s 977 s 1.95 ms 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 3.90 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 7.82 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 15.6 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms 31.2 ms remarks 1. f w : watch timer clock frequency (f x /2 7 , f xt , or f xt /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 8.2 watch timer configuration the watch timer includes the following hardware. table 8-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 9 bits 1 control registers watch timer mode control register (wtm) watch timer interrupt time selection register (wtim) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 8 watch timer user ? s manual u15400ej3v0ud 163 8.3 control registers for watch timer the watch timer is controlled by the following registers. ? watch timer mode control register (wtm) ? watch timer interrupt time selection register (wtim) (1) watch timer mode control register (wtm) this register is used to control the watch timer count clock, operation enable/disable status, prescaler interval time, and the 5-bit counter operation. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 8-2. format of watch timer mode control register symbol 7 6 5 4 3 2 <1> <0> address after reset r/w wtm wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 ff4ah 00h r/w wtm7 selection of watch timer count clock (f w ) 0 f x /2 7 (39.1 khz) 1f xt (32.768 khz) or f xt /2 (16.384 khz) note wtm6 wtm5 wtm4 selection of prescaler interval time 000 2 4 /f w 001 2 5 /f w 010 2 6 /f w 011 2 7 /f w 100 2 8 /f w 101 2 9 /f w other than above setting prohibited wtm1 control of 5-bit counter operation 0 cleared after stopping operation 1start wtm0 watch timer operation enable/disable 0 operation stopped (prescaler and timer are both cleared) 1 operation enabled note this is the frequency (f xt or f xt /2) set via the watch timer interrupt time selection register (wtim). remarks 1. f w : watch timer clock frequency (f x /2 7 , f xt , or f xt /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 8 watch timer user ? s manual u15400ej3v0ud 164 (2) watch timer interrupt time selection register (wtim) this register is used to set the interrupt time by selecting either the source clock or the clock divided by 2 for the subsystem clock to be input to watch timer. wtim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 8-3. format of watch timer interrupt time selection register symbol 7 6 5 4 3 2 1 <0> address after reset r/w wtim0000000wtsff4bh00hr/w wts selection of watch timer interrupt time note 0 0.5 s (f xt ) 1 1.0 s (f xt /2) note the selection is only available when bit 7 (wtm7) of the watch timer mode control register (wtm) is 1. remark f xt : subsystem clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 8 watch timer user ? s manual u15400ej3v0ud 165 8.4 watch timer operation 8.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used to enable the watch timer to operate at 0.5-second intervals. also, an interrupt request (intwt) occurs at an interval of 1.0 seconds when using the 32.768 khz subsystem clock via a setting in the watch timer interrupt time selection register (wtim). the watch timer is used to generate an interrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch timer mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. it is possible to start the watch timer from zero seconds by clearing wtm1 to 0 when the interval timer and watch timer operate at the same time. in this case, however, an error of up to 2 9 1/f w seconds may occur in the overflow (intwt) after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0. 8.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value. the interval can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 8-3. interval time of interval timer wtm6 wtm5 wtm4 interval time at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz at f xt = 16.384 khz 0002 4 1/f w 409.6 s 488 s 488 s 976 s 0012 5 1/f w 819.2 s 977 s 977 s 1.95 ms 0102 6 1/f w 1.64 ms 1.95 ms 1.95 ms 3.90 ms 0112 7 1/f w 3.28 ms 3.91 ms 3.91 ms 7.82 ms 1002 8 1/f w 6.55 ms 7.81 ms 7.81 ms 15.6 ms 1012 9 1/f w 13.1 ms 15.6 ms 15.6 ms 31.2 ms other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 8 watch timer user ? s manual u15400ej3v0ud 166 figure 8-4. watch timer/interval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval time (t) t caution when operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (wtm0) of the watch timer mode control register (wtm) to 1, the interval until the first interrupt request (intwt) is generated after the register is set does not exactly match the watch timer interrupt time (0.5 s). this is because there is a delay of one 9-bit prescaler output cycle until the 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. remarks 1. f w : watch timer clock frequency 2. the parenthesized values apply to operation at f w = 32.768 khz. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 167 chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect a program loop. when a program loop is detected, a non-maskable interrupt or the reset signal can be generated. table 9-1. watchdog timer program loop detection time program loop detection time at f x = 5.0 mhz 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at an arbitrary preset interval. table 9-2. interval time interval at f x = 5.0 mhz 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 9 watchdog timer user?s manual u15400ej3v0ud 168 9.2 watchdog timer configuration the watchdog timer includes the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) figure 9-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 3 7-bit counter wdtif wdtmk wdcs2 wdcs1 wdcs0 watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) clear wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 9 watchdog timer user ? s manual u15400ej3v0ud 169 9.3 watchdog timer control registers the watchdog timer is controlled by the following two registers. watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock selection register (wdcs) this register sets the watchdog timer count clock. wdcs is set with an 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 9-2. format of watchdog timer clock selection register wdcs2 0 0 1 1 wdcs1 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) wdcs0 0 0 0 0 setting prohibited other than above watchdog timer count clock selection 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x (410 s) (1.64 ms) (6.55 ms) (26.2 ms) interval 0 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs 76 54 symbol address after reset r/w ff42h 00h r/w 3210 remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 9 watchdog timer user ? s manual u15400ej3v0ud 170 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3. format of watchdog timer mode register notes 1. once run has been set (1), it cannot be cleared (0) by software. therefore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set (1), they cannot be cleared (0) by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock selection register (wdcs). 2. to set watchdog timer mode 1 or 2, set wdtm4 to 1 after confirming wdtif (bit 0 of interrupt request flag register 0 (if0)) is set to 0. when watchdog timer mode 1 or 2 is selected with wdtif set to 1, a non-maskable interrupt is generated upon the completion of rewriting wdtm4. run 0 1 watchdog timer operation selection note 1 stop counting. clear counter and start counting. wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (a maskable interrupt is generated upon overflow occurrence) note 3 watchdog timer mode 1 (a non-maskable interrupt is generated upon overflow occurrence) watchdog timer mode 2 (a reset operation is started upon overflow occurrence) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 9 watchdog timer user ? s manual u15400ej3v0ud 171 9.4 watchdog timer operation 9.4.1 operation as watchdog timer the watchdog timer detects a program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (wdcs0 to wdcs2) of watchdog timer clock selection register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set program loop detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start counting. if run is not set to 1, and the program loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before executing the stop instruction. cautions 1. the actual program loop detection time may be up to 0.8% shorter than the set time. 2. when the subsystem clock is selected as the cpu clock, the watchdog timer count operation is stopped. even when the main system clock continues oscillating in this case, watchdog timer count operation is stopped. table 9-4. watchdog timer program loop detection time wdcs2 wdcs1 wdcs0 program loop detection time at f x = 5.0 mhz 0002 11 1/f x 410 s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 9 watchdog timer user ? s manual u15400ej3v0ud 172 9.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. select a count clock (or interval) by setting bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock selection register (wdcs). the watchdog timer starts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (wdtmk) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before executing the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless the reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 9-5. interval time of interval timer wdcs2 wdcs1 wdcs0 interval at f x = 5.0 mhz 0002 11 1/f x 410 s 0102 13 1/f x 1.64 ms 1002 15 1/f x 6.55 ms 1102 17 1/f x 26.2 ms f x : main system clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 173 chapter 10 8-bit a/d converter 10.1 8-bit a/d converter functions the 8-bit a/d converter is a 8-bit resolution converter used to convert analog inputs into digital signals. this converter can control eight channels (ani0 to ani7) of analog inputs. a/d conversion can only be started by software. one of analog inputs ani0 to ani7 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time a/d conversion is complete. a conversion operation is also possible using the subsystem clock multiplied by 4 (131 khz). caution a/d conversion is stopped in the halt and stop modes. 10.2 8-bit a/d converter configuration the 8-bit a/d converter includes the following hardware. table 10-1. configuration of 8-bit a/d converter item configuration analog inputs 8 channels (ani0 to ani7) registers successive approximation register (sar) a/d conversion result register 0 (adcrl0) control registers a/d converter mode register 0 (adml0) a/d converter mode register 1 (adml1) analog input channel specification register 0 (ads0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 174 user?s manual u15400ej3v0ud figure 10-1. block diagram of 8-bit a/d converter (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcrl0). (2) a/d conversion result register 0 (adcrl0) adcrl0 is an 8-bit register that holds the result of a/d conversion. each time a/d conversion ends, the conversion result in the successive approximation register is loaded into adcrl0. the results are stored in adcrl0 from the highest bit. adcrl0 can be read with an 8-bit memory manipulation instruction. reset input sets adcrl0 to 00h. adcrl0 symbol 7 ff15h address after reset 00h r/w r 6543210 (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. ani3/p63 sample & hold circuit voltage comparator successive approximation register (sar) controller a/d conversion result register 0 (adcrl0) av ss intad0 a/d converter mode register 0 (adml0) internal bus v ss adcs0 fr02 fr01 fr00 ads01 p-ch av dd analog input channel specification register 0 (ads0) ads00 ads02 adce0 ani2/p62 ani5/p65 ani4/p64 ani1/p61 ani0/p60 ani7/p67 ani6/p66 adsel1 a/d converter mode register 1 (adml1) selector tap selector www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter user ? s manual u15400ej3v0ud 175 (5) series resistor string the series resistor string is configured between av dd and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani7 the ani0 to ani7 pins are the 8-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply the ani0 to ani7 pins with voltages that fall outside the rated range. if a voltage greater than or equal to av dd or less than or equal to av ss (even if within the absolute maximum ratings) is applied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ss pin the av ss pin is the ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d converter is not being used. (8) av dd pin the av dd pin is the analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd pin, even while the a/d converter is not being used. (9) band-gap circuit the band-gap circuit activates the reference voltage inside the comparator prior to a/d conversion. start conversion after 14 s have elapsed following the activation of the band-gap circuit. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 176 user ? s manual u15400ej3v0ud 10.3 8-bit a/d converter control registers the 8-bit a/d converter is controlled by the following three registers. a/d converter mode register 0 (adml0) a/d converter mode register 1 (adml1) analog input channel specification register 0 (ads0) (1) a/d converter mode register 0 (adml0) adml0 specifies the a/d conversion time for analog inputs. it also specifies whether to enable conversion. adml0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adml0 to 00h. figure 10-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 1 a/d conversion time selection note 1 adsel1 0 0 0 0 0 0 1 144/f x 120/f x 96/f x 72/f x 60/f x 48/f x a/d conversion using subsystem clock multiplied by 4 note 3 (conversion time is undefined) fr02 0 0 0 1 1 1 (28.8 s) (24.0 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) fr01 0 0 1 0 0 1 fr00 0 1 0 0 1 0 other than above conversion disabled conversion enabled control of band-gap circuit adce0 0 1 band-gap circuit stopped band-gap circuit operating setting prohibited adcs0 0 fr02 fr01 fr00 0 0 adce0 adml0 <7> 6 5 4 symbol address after reset r/w ff80h 00h r/w 3210 notes 1. the selection of the a/d conversion time is set using a combination of both the adml0 and adml1 registers. be sure to set these bits so that the a/d conversion time is at least 14 s. 2. these bit combinations must not be set, as the a/d conversion time will fall below 14 s at f x = 5.0 mhz. 3. when using the subsystem clock multiplied by 4, enable the 4 multiplication circuit using a mask option or the subclock selection register. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter user ? s manual u15400ej3v0ud 177 remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. cautions 1. start conversion (adcs0 = 1) after 14 s have elapsed following the setting of adce0. if adce0 is not used, the conversion result immediately after the setting of adcs0 is undefined. 2. the conversion result may be undefined after adcs0 has been cleared to 0. to read the conversion result, perform the read operation during a/d conversion. if the conversion result needs to be read after a/d conversion has been stopped, stop the a/d conversion operation before the end of the next a/d conversion. 3. always set bits 1, 2, and 6 to 0. (2) a/d converter mode register 1 (adml1) this register is used to perform a/d conversion using the subsystem clock multiplied by 4. adml1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adml1 to 00h. figure 10-3. format of a/d converter mode register 1 notes 1. the selection of the a/d conversion time is set using a combination of both the adml0 and adml1 registers. be sure to set these bits so that the a/d conversion time is at least 14 s. 2. these bit combinations must not be set, as the a/d conversion time will fall below 14 s at f x = 5.0 mhz. 3. when using the subsystem clock multiplied by 4, enable the 4 multiplication circuit using a mask option or the subclock selection register. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. a/d conversion time selection note 1 adsel1 0 0 0 0 0 0 1 144/f x 120/f x 96/f x 72/f x 60/f x 48/f x a/d conversion using subsystem clock multiplied by 4 note 3 (conversion time is undefined) fr02 0 0 0 1 1 1 (28.8 s) (24.0 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) fr01 0 0 1 0 0 1 fr00 0 1 0 0 1 0 other than above setting prohibited adsel1 0 0 0 0 0 0 0 adml1 <7> 6 5 4 symbol address after reset r/w ff81h 00h r/w 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 178 user ? s manual u15400ej3v0ud (3) analog input channel specification register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 10-4. format of analog input channel specification register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ads02 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads01 0 0 1 1 0 0 1 1 ads00 0 1 0 1 0 1 0 1 caution bits 3 to 7 must be set to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter user ? s manual u15400ej3v0ud 179 10.4 8-bit a/d converter operation 10.4.1 basic operation of 8-bit a/d converter <1> bit 0 of a/d converter mode register 0 (adml0) is set (adce0 = 1). <2> select a channel for a/d conversion, using analog input channel specification register 0 (ads0). <3> when 14 s or more have elapsed after adce0 was set, set bit 7 of adml0 (adcs0 = 1). the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <4> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <5> bit 7 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av dd . <6> the series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av dd , the msb of sar is left set. if it is lower than half of av dd , the msb is reset. <7> bit 6 of sar is set automatically, and comparison shifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows. ? bit 7 = 1: three quarters of av dd ? bit 7 = 0: one quarter of av dd the tap voltage is compared with the analog input voltage. bit 6 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 6 = 1 ? analog input voltage < tap voltage: bit 6 = 0 <8> comparison is repeated until bit 0 of sar is reached. <9> when comparison is completed for all of the 8 bits, a significant digital result is left in sar. this value is sent to and latched in a/d conversion result register 0 (adcrl0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. start conversion (adcs0 = 1) after 14 s have elapsed following the setting of adce0. if adce0 is not used, the conversion result immediately after the setting of adcs0 is undefined. 2. in standby mode, a/d converter operation is stopped. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 180 user ? s manual u15400ej3v0ud figure 10-5. basic operation of 8-bit a/d converter a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adml0) is reset (0) by software. if an attempt is made to write to adml0 or analog input channel specification register 0 (ads0) during a/d conversion, the a/d conversion in progress is canceled. in this case, a/d conversion is restarted from the beginning, if adcs0 is set (1). reset input clears a/d conversion result register 0 (adcrl0) to 00h. 10.4.2 input voltage and conversion result the relationship between the analog input voltage at the analog input pins (ani0 to ani7) and the a/d conversion result (a/d conversion result register 0 (adcrl0)) is represented by: adcrl0 = int ( 256 + 0.5) or (adcrl0 ? 0.5) v in < (adcrl0 + 0.5) int( ): function that returns the integer part of a parenthesized value v in : analog input voltage av dd : supply voltage for the a/d converter adcrl0: value in a/d conversion result register 0 (adcrl0) figure 10-6 shows the relationship between the analog input voltage and the a/d conversion result. v in av dd av dd 256 av dd 256 conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcrl0 intad0 c0h or 40h 80h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter user ? s manual u15400ej3v0ud 181 figure 10-6. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcrl0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 182 user ? s manual u15400ej3v0ud 10.4.3 operation mode of 8-bit a/d converter the a/d converter is initially in select mode. in this mode, analog input channel specification register 0 (ads0) is used to select an analog input channel from ani0 to ani7 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adml0). the a/d conversion result is saved to a/d conversion result register 0 (adcrl0). at the same time, an interrupt request signal (intad0) is generated. ? ? ? ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adml0) to 1 triggers a/d conversion for the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result register 0 (adcrl0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adml0. if data where adcs0 is 1 is written to adml0 again during a/d conversion, the a/d conversion in progress is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adml0 again during a/d conversion, a/d conversion is stopped immediately. figure 10-7. software-started a/d conversion rewriting adml0 adcs0 = 1 rewriting adml0 adcs0 = 1 adcs0 = 0 a/d conversion adcrl0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 7 2. m = 0 to 7 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter user ? s manual u15400ej3v0ud 183 10.5 cautions related to 8-bit a/d converter (1) power consumption in standby mode in standby mode, the a/d converter stops operation. clearing bit 7 (adcs0) of a/d converter mode register 0 (adml0) to 0 can reduce the power consumption. figure 10-8 shows how to reduce the power consumption in standby mode. figure 10-8. how to reduce power consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for pins ani0 to ani7 be sure to keep the input voltage at ani0 to ani7 within the rating. if a voltage greater than or equal to av dd or less than or equal to av ss (even within the absolute maximum ratings) is input into a conversion channel, the conversion output of the channel becomes undefined, which may affect the conversion output of the other channels. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcrl0) at the end of conversion and reading from adcrl0 using instruction reading from adcrl0 takes precedence. after reading, the new conversion result is written to adcrl0. <2> conflict between writing to adcrl0 at the end of conversion and writing to a/d converter mode register 0 (adml0) or analog input channel specification register 0 (ads0) writing to adml0 or ads0 takes precedence. adcrl0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediately after start of a/d conversion if the band-gap circuit is not used (adce0 = 0) or conversion is started before 14 s have elapsed following the setting of adce, only the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0), drop the first conversion result and use the second and subsequent conversion results. when 14 s have elapsed following the activation of the band-gap circuit (adce0 = 1), the first conversion value is normal. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 184 user ? s manual u15400ej3v0ud (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the completion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operation is completed. figures 10-9 and 10-10 show the timing at which the conversion result is read. figure 10-9. conversion result read timing (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcrl0 intad0 adcs0 figure 10-10. conversion result read timing (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcrl0 intad0 adcs0 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter user ? s manual u15400ej3v0ud 185 (6) noise prevention to maintain a resolution of 8 bits, watch for noise at the av dd and ani0 to ani7 pins. the higher the output impedance of the analog input source, the larger the effect by noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 10-11. figure 10-11. analog input pin treatment (7) ani0 to ani7 the analog input pins (ani0 to ani7) are alternate-function pins. they are also used as port pins (p60 to p67). if any of ani0 to ani7 has been selected for a/d conversion, do not execute input instructions for the ports; otherwise the conversion resolution may be reduced. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur that prevents an a/d conversion result from being obtained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) input impedance of ani0 to ani7 pins this a/d converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampling, only the leak current flows. during sampling, the current for charging the capacitor also flows, so the input impedance fluctuates and has no meaning. however, to ensure adequate sampling, it is recommended that the output impedance of the analog input source be set to 10 k ? or lower, or a capacitor of about 100 pf be connected to the ani0 to ani7 pins (see figure 10-11 ). c = 100 to 1,000 pf if noise greater than or equal to av dd or less than or equal to av ss is likely to come to the ani0 to ani7 pins, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd ani0 to ani7 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 10 8-bit a/d converter 186 user ? s manual u15400ej3v0ud (9) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adml0) does not clear the interrupt request flag (adif0). if the analog input pins are changed during a/d conversion, therefore, the a/d conversion result and the conversion end interrupt request flag may be set for the previous analog input immediately before rewriting adml0. in this case, adif0 may already be set if it is read-accessed immediately after adml0 is rewritten, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is restarted, adif0 must be cleared beforehand. figure 10-12. a/d conversion end interrupt request generation timing remarks 1. n = 0 to 7 2. m = 0 to 7 (10) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani7 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as the v dd pin, as shown in figure 10-13. figure 10-13. av dd pin handling main power supply backup capacitor v dd av dd v ss av ss (11) av dd pin input impedance a series resistor string of several tens of k ? is connected between the av dd and av ss pins. consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a series connection with the series resistor string, creating a large reference voltage differential. a/d conversion adcrl0 intad0 rewriting adml0 (to begin conversion for anin) rewriting adml0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. anin anin anim anim anin anin anim anim www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 187 chapter 11 serial interface 20 11.1 serial interface 20 functions serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains a uart-dedicated baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud rates by dividing the frequency of the clock input to the asck20 pin. (3) 3-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock line (sck20) and two serial data lines (si20 and so20). as it supports simultaneous transmission and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchronous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bit data transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75xl, 78k, and 17k series devices. 11.2 serial interface 20 configuration serial interface 20 includes the following hardware. table 11-1. configuration of serial interface 20 item configuration registers transmit shift register 20 (txs20) receive shift register 20 (rxs20) receive buffer register 20 (rxb20) control registers serial operation mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20) port mode register 2 (pm2) port 2 (p2) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 188 figure 11-1. block diagram of serial interface 20 internal bus receive buffer register 20 (rxb20) switch of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) receive shift register 20 (rxs20) csie20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmit shift register 20 (txs20) transmit shift clock selector csie20 dap20 data phase control receive shift clock si20/p22 /rxd20 so20/p21 /txd20 4 parity detection detection of stop bit receive data counter parity operation addition of stop bit transmit data counter sl20, cl20, ps200, ps201 reception enable receive clock detection clock detection of start bit port mode register (pm21) csie20 csck20 sck20/p20 /asck20 receive detection internal clock output external clock input transmit/receive clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus clock phase control note see figure11-2 for the configuration of the baud rate generator. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 189 figure 11-2. block diagram of baud rate generator 20 clock for receive detection transmit shift clock receive shift clock receive detection txe20 rxe20 csie20 1/2 1/2 transmit clock counter (3 bits) receive clock counter (3 bits) 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 asck20/sck20/p20 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus selector selector selector www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 190 (1) transmit shift register 20 (txs20) txs20 is a register in which transmit data is prepared. the transmit data is output from txs20 bit-serially. when the data length is seven bits, bits 0 to 6 of the data in txs20 will be transmit data. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory manipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and receive buffer register 20 (rxb20) are mapped at the same address, so any attempt to read from txs20 results in a value being read from rxb20. (2) receive shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the receive data to receive buffer register 20 (rxb20). rxs20 cannot be manipulated directly by a program. (3) receive buffer register 20 (rxb20) rxb20 holds receive data. new receive data is transferred from receive shift register 20 (rxs20) at every 1-byte data reception. when the data length is seven bits, the receive data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipulation instruction, but cannot be written. reset input makes rxb20 undefined. caution rxb20 and transmit shift register 20 (txs20) are mapped at the same address, so any attempt to write to rxb20 results in a value being written to txs20. (4) transmit controller the transmit controller controls transmission. for example, it adds start, parity, and stop bits to the data in transmit shift register 20 (txs20), according to the setting of asynchronous serial interface mode register 20 (asim20). (5) receive controller the receive controller controls reception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during reception. if an error is detected, asynchronous serial interface status register 20 (asis20) is set according to the status of the error. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 191 11.3 serial interface 20 control registers serial interface 20 is controlled by the following six registers. ? serial operation mode register 20 (csim20) ? asynchronous serial interface mode register 20 (asim20) ? asynchronous serial interface status register 20 (asis20) ? baud rate generator control register 20 (brgc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 20 (csim20) csim20 is used to make the settings related to 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. figure 11-3. format of serial operation mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 0 000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator cautions 1. bits 0 and 3 to 6 must be set to 0. 2. csim20 must be cleared to 00h if uart mode is selected. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 192 (2) asynchronous serial interface mode register 20 (asim20) asim20 is used to make the settings related to asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. figure 11-4. format of asynchronous serial interface mode register 20 cautions 1. bits 0 and 1 must be set to 0. 2. if 3-wire serial i/o mode is selected, asim20 must be set to 00h. 3. switch operation modes after halting the serial transmission/reception operation. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled rxe20 0 1 receive operation control receive operation stopped receive operation enabled ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 193 table 11-2. serial interface 20 operation mode settings (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 00 0 note 1 note 1 note 1 note 1 note 1 note 1 ?? p22 p21 p20 other than above setting prohibited (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 01 external clock sck20 input 10 101 msb internal clock sck20 output 01 external clock sck20 input 00 11 1 1 note 2 note 2 01 01 lsb internal clock si20 note 2 so20 (cmos output) sck20 output other than above setting prohibited (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 1 external clock asck20 input 10000 note 1 note 1 01 note 1 note 1 internal clock p22 txd20 (cmos output) p20 1 external clock asck20 input 010001 note 1 note 1 note 1 note 1 internal clock p21 p20 1 external clock asck20 input 110001 01 note 1 note 1 lsb internal clock rxd20 txd20 (cmos output) p20 other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p22 (cmos i/o). remark : don ? t care www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 194 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. asis20 is set with a 1-bit or 8-bit memory manipulation instruction. the contents of asis20 are undefined in 3-wire serial i/o mode. reset input sets asis20 to 00h. figure 11-5. format of asynchronous serial interface status register 20 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, an overrun error will occur every time data is received. pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543<2><1><0> no parity error occurred. a parity error occurred (when the transmit parity and receive parity did not match). fe20 0 1 framing error flag no framing error occurred. a framing error occurred (when stop bit was not detected). note 1 ove20 0 1 overrun error flag no overrun error occurred. an overrun error occurred note 2 (when the next receive operation was completed before the data was read from receive buffer register 20). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 195 (4) baud rate generator control register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. figure 11-6. format of baud rate generator control register 20 note an external clock can be used only in uart mode. cautions 1. when writing to brgc20 during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. tps203 0 0 0 0 0 0 0 0 1 selection of baud rate generator source clock tps203 tps202 tps201 tps200 0000 brgc20 symbol address after reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock input to the asck20 pin note setting prohibited (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) other than above tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 196 the baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal scaled obtained by dividing the clock input to the asck20 pin. (a) generation of baud rate transmit/receive clock from system clock the transmit/receive clock is generated by dividing the system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency n: values in figure 11-6, determined by the values of tps200 to tps203 (2 n 8) table 11-3. example of relationship between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1 8 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 197 (b) generation of baud rate transmit/receive clock from external clock input to asck20 pin the transmit/receive clock is generated by dividing the clock input from the asck20 pin. the baud rate of a clock generated from the clock input to the asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to the asck20 pin table 11-4. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) generation of serial clock from system clock in 3-wire serial i/o mode the serial clock is generated by dividing the system clock. the frequency of the serial clock can be obtained by the following expression. if the serial clock is externally input to the sck20 pin, setting brgc20 is not necessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n: values in figure 11-6 determined by the settings of tps200 to tps203 (1 n 8) f asck 16 f x 2 n + 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 198 11.4 serial interface 20 operation serial interface 20 provides the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 11.4.1 operation stop mode in operation stop mode, serial transfer is not executed, thereby reducing the power consumption. the p20/sck20/asck20, p21/so20/txd20, and p22/si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode operation disabled operation enabled csie20 0 0 0 0 dir20 csck20 0 csim20 <7> 6 5 4 symbol address after reset r/w ff72h 00h r/w 3210 caution bits 0 and 3 to 6 must be set to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 199 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 receive operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 caution bits 0 and 1 must be set to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user?s manual u15400ej3v0ud 200 11.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. this device incorporates a uart-dedicated baud rate generator that enables communications at the desired baud rate. in addition, the baud rate can also be defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the midi standard. (1) register setting uart mode is set by serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), asynchronous serial interface status register 20 (asis20), and baud rate generator control register 20 (brgc20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. set csim20 to 00h when uart mode is selected. caution bits 0 and 3 to 6 must be set to 0. csie20 0 1 3-wire serial i/o mode operation control csie20 0 000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator dir20 0 1 first-bit specification msb lsb www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 201 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. cautions 1. bits 0 and 1 must be set to 0. 2. switch operation modes after halting the serial transmission/reception operation. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 202 (c) asynchronous serial interface status register 20 (asis20) asis20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asis20 to 00h. notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, an overrun error will occur every time data is received. pe20 0 1 parity error flag no parity error occured a parity error occured (when the parity of transmit data did not match) no framing error occured a framing error occured (when stop bit was not detected) note 1 no overrun error occured an overrun error occured note 2 (when the next receive operation was completed before data was read from reception buffer register 20) fe20 0 1 0 1 framing error flag overrun error flag ove20 0 0 0 0 0 pe20 fe20 ove20 asis20 76 54 symbol address after reset r/w ff71h 00h r 3 <2> <1> <0> www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 203 (d) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. note can only be used in the uart mode. cautions 1. when writing to brgc20 during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range in the uart mode. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. the baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal obtained by dividing the clock input to the asck20 pin. (i) generation of baud rate transmit/receive clock from system clock the transmit/receive clock is generated by dividing the system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency n: values in the above table determined by the settings of tps200 to tps203 (2 n 8) f x 2 n + 1 8 tps203 0 0 0 0 0 0 0 0 1 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? setting prohibited selection of baud rate generator source clock external clock input to asck20 pin note other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 204 table 11-5. example of relationship between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x = 5.0 mhz because the resulting baud rate exceeds the rated range. (ii) generation of baud rate transmit/receive clock from external clock input to asck20 pin the transmit/receive clock is generated by dividing the clock input from the asck20 pin. the baud rate of a clock generated from the clock input to the asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to asck20 pin table 11-6. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 205 (2) communication operation (a) data format the transmit/receive data format is as shown in figure 11-7. one data frame consists of a start bit, character bits, parity bit, and stop bit(s). the specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out using asynchronous serial interface mode register 20 (asim20). figure 11-7. format of asynchronous serial interface transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bits .................. 1 bit ? character bits ........... 7 bits/8 bits ? parity bits.................. even parity/odd parity/0 parity/no parity ? stop bits.................... 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always ? 0 ? . the serial transfer rate is selected by baud rate generator control register 20 (brgc20). if a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (asis20). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 206 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a one-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity ? ? ? ? at transmission the parity bit is determined so that the number of bits with a value of ? 1 ? in the transmit data including the parity bit is even. the parity bit value should be as follows. the number of bits with a value of ? 1 ? is an odd number in transmit data: 1 the number of bits with a value of ? 1 ? is an even number in transmit data: 0 ? ? ? ? at reception the number of bits with a value of ? 1 ? in the receive data including parity bit is counted, and if the number is odd, a parity error occurs. (ii) odd parity ? ? ? ? at transmission opposite to even parity, the parity bit is determined so that the number of bits with a value of ? 1 ? in the transmit data including parity bit is odd. the parity bit value should be as follows. the number of bits with a value of ? 1 ? is an odd number in transmit data: 0 the number of bits with a value of ? 1 ? is an even number in transmit data: 1 ? ? ? ? at reception the number of bits with a value of ? 1 ? in the receive data including parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to ? 0 ? irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error does not occur, irrespective of whether the parity bit is set to ? 0 ? or ? 1 ? . (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error does not occur. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 207 (c) transmission a transmit operation is started by writing transmit data to transmit shift register 20 (txs20). the start bit, parity bit, and stop bit(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interrupt (intst20) is generated. figure 11-8. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite asynchronous serial interface mode register 20 (asim20) during a transmit operation. if the asim20 register is rewritten during transmission, subsequent transmission may not be able to be performed (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 208 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set (1), a receive operation is enabled and sampling of the rxd20 pin input is performed. rxd20 pin input sampling is performed using the serial clock specified by brgc20. when the rxd20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 20 (rxb20), and a reception completion interrupt (intsr20) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr20 is not generated. figure 11-9. asynchronous serial interface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read receive buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 209 (e) receive errors the following three errors may occur during a receive operation: a parity error, framing error, and overrun error. after data reception, an error flag is set in asynchronous serial interface status register 20 (asis20). receive error causes are shown in table 11-7. it is possible to determine what kind of error occurred during reception by reading the contents of asis20 in the reception error interrupt servicing (see table 11-7 and figure 11-10 ). the contents of asis20 are reset (0) by reading receive buffer register 20 (rxb20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 11-7. receive error causes receive errors cause asis20 value parity error parity at transmission and reception do not match 04h framing error stop bit not detected 02h overrun error reception of next data is completed before data is read from receive buffer register 01h figure 11-10. receive error timing (a) parity error occurrence stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error occurrence stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 register are reset (0) by reading receive buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read receive buffer register 20 (rxb20) also when a receive error occurs. if rxb20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 210 (f) reading receive data when the reception completion interrupt (intsr20) occurs, receive data can be read by reading the value of receive buffer register 20 (rxb20). to read the receive data stored in receive buffer register 20 (rxb20), read while reception is enabled (rxe20 = 1). remark however, if it is necessary to read receive data after reception has stopped (rxe20 = 0), read using either of the following methods. (a) read after setting rxe20 = 0 after waiting for one cycle or more of the source clock selected by brgc20. (b) read after bit 2 (dir20) of serial operation mode register 20 (csim20) is set (1). program example of (a) (brgc20 = 00h (source clock = fx/2)) intrex: ; nop ;2 clocks clr1 rxe20 ;reception stopped mov a, rxb20 ;read receive data program example of (b) intrxe: ; set1 csim20.2 ;dir20 flag is set to lsb first clr1 rxe20 ;reception stopped mov a, rxb20 ;read receive data www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 211 (3) cautions related to uart mode (a) when bit 7 (txe20) of asynchronous serial interface mode register 20 (asim20) is cleared during transmission, be sure to set transmit shift register 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is cleared during reception, receive buffer register 20 (rxb20) and the receive completion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at the time indicated by <1> , rxb20 holds the previous data and intsr20 is not generated. when rxe20 is set to 0 at the time indicated by <2> , rxb20 renews the data and intsr20 is not generated. when rxe20 is set to 0 at the time indicated by <3> , rxb20 renews the data and intsr20 is generated. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 212 11.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. communication is performed using three lines: a serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed using serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), and baud rate generator control register 20 (brgc20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 0 000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator caution bits 0 and 3 to 6 must be set to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 213 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. when 3-wire serial i/o mode is selected, asim20 must be set to 00h. cautions 1. bits 0 and 1 must be set to 0. 2. switch operation modes after halting the serial transmission/reception operation. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error occurs). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 transmit data character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 214 (c) baud rate generator control register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. caution when writing to brgc20 during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. if the internal clock is used as the serial clock for 3-wire serial i/o mode, set bits tps200 to tps203 to set the frequency of the serial clock. to obtain the frequency to be set, use the following expression. when an external clock is input to the sck20 pin, setting brgc20 is not necessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n: values in the above table determined by the settings of tps200 to tps203 (1 n 8) f x 2 n + 1 tps203 0 0 0 0 0 0 0 0 tps202 0 0 0 0 1 1 1 1 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 tps200 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 setting prohibited selection of baud rate generator source clock other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 215 (2) communication operation in 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/ received bit by bit in synchronization with the serial clock. transmit shift register 20 (txs20/sio20) and receive shift register 20 (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). then transmit data is held in the so20 latch and output from the so20 pin. also, receive data input to the si20 pin is latched in receive buffer register 20 (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/sio20 and rxs20 stops automatically, and the interrupt request signal (intcsi20) is generated. figure 11-11. 3-wire serial i/o mode timing (1/2) (i) master operation timing 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 11 serial interface 20 user ? s manual u15400ej3v0ud 216 figure 11-11. 3-wire serial i/o mode timing (2/2) (ii) slave operation timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (3) transfer start serial transfer is started by setting transfer data to transmit shift register 20 (txs20/sio20) when the following two conditions are satisfied. ? bit 7 (csie20) of serial operation mode register 20 (csim20) = 1 ? internal serial clock is stopped or sck20 is high after 8-bit serial transfer. caution if csie20 is set to ?1? after data is written to txs20/sio20, transfer does not start. termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (intcsi20). www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 217 chapter 12 serial interface 1a0 12.1 function of serial interface 1a0 serial interface 1a0 has the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode is used when serial transfer will not be performed. it enables a reduction in power consumption. (2) 3-wire serial i/o mode (msb/lsb-first switchable) this mode is used to transfer 8-bit data using three lines: a serial clock line (sck10) and two serial data lines (si10 and so10). because this mode supports simultaneous transmission and reception, 3-wire serial i/o mode requires less processing time for data transfer. also, when using 3-wire serial i/o mode, it is possible to select whether 8-bit data transfer will start with the msb or lsb, so any device can be connected regardless of whether that device is designed for msb-first or lsb-first transfers. 3-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers with conventional clocked serial interfaces, such as those found in the 75xl series, 78k series, and 17k series. (3) 3-wire serial mode with automatic transmit/receive function (msb/lsb-first switchable) this mode has an automatic transmit/receive function in addition to the functions in (2) above. the automatic transmit/receive function is used to transmit/receive data with a maximum of 16 bytes. this function enables the hardware to transmit/receive data to/from the osd (on screen display) device and a device with an on-chip display controller/driver independently of the cpu, thus alleviating the software load. 12.2 configuration of serial interface 1a0 serial interface 1a0 includes the following hardware. table 12-1. configuration of serial interface 1a0 item configuration registers serial i/o shift register 1a0 (sio1a0) automatic data transmit/receive address pointer 0 (adtp0) control registers serial operation mode register 1a0 (csim1a0) automatic data transmit/receive control register 0 (adtc0) automatic data transmit/receive interval specification register 0 (adti0) port mode register 2 (pm2) port 2 (p2) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user?s manual u15400ej3v0ud 218 figure 12-1. block diagram of serial interface 1a0 re0 arld 0 trf0 internal bus automatic data transmit/receive control register 0 (adtc0) serial operation mode register 1a0 (csim1a0) adti 07 adti 04 adti 03 adti 02 adti 01 adti 00 5-bit counter serial i/o shift register 1a0 (sio1a0) hand shake serial clock counter selector so10/ p24 pm24 p24 output latch dir 10 dir 10 buffer ram automatic data transmit/receive address pointer 0 (adtp0) pm23 trf0 p23 output latch match adti00 to adti04 intcsi10 clear f sck sio1a0 write q r s selector arld0 csie 10 dir 10 ate0 scl 101 scl 100 ate0 si10/ p25 automatic data transmit/receive interval specification register 0 (adti0) /2 2 f x /2 3 f x /2 4 f x sck10/ p23 lsck 10 selector lsck 10 csie10 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 219 (1) serial i/o shift register 1a0 (sio1a0) this is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/reception in synchronization with the serial clock. sio1a0 is set with an 8-bit memory manipulation instruction. when the value in bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) is 1, writing data to sio1a0 starts a serial operation. during transmission, data written to sio1a0 is output to the serial output (so10). during reception, data is read from the serial input (si10) to sio1a0. reset input sets sio1a0 to 00h. caution do not write data to sio1a0 while the automatic transmit/receive function is activated. (2) automatic data transmit/receive address pointer 0 (adtp0) this register stores value of (transmit data byte ? 1) while the automatic transmit/receive function is activated. as data is transferred/received, it is automatically decremented. adtp0 is set with an 8-bit memory manipulation instruction. the higher 4 bits must be set to 0. reset input makes adtp0 undefined. caution do not write data to adtp0 while the automatic transmit/receive function is activated. (3) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 220 12.3 control registers for serial interface 1a0 serial interface 1a0 is controlled by the following five registers. ? serial operation mode register 1a0 (csim1a0) ? automatic data transmit/receive control register 0 (adtc0) ? automatic data transmit/receive interval specification register 0 (adti0) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 1a0 (csim1a0) this register sets serial interface 1a0 serial clock, operation mode, operation enable/disable, and automatic transmission/reception operation enable/disable. csim1a0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. caution set the port mode register (pm ) in the 3-wire serial i/o mode as follows. set the output latch to 0. ? in the case of serial clock output (master transmission or master reception) set the sck10/p23 pin to output mode (pm23 = 0). in the case of serial clock input (slave transmission or slave reception) set the sck10/p23 pin to input mode (pm23 = 1). in transmission or transmission/reception mode set the so10/p24 pin to output mode (pm24 = 0). set the si10/p25 pin to input mode (pm25 = 1). in reception mode set the si10/p25 pin to input mode (pm25 = 1). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 221 figure 12-2. format of serial operation mode register 1a0 symbol <7> 6 <5> <4> 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operation serial counter port note 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function dir10 specification of first bit of serial transfer data 0msb 1lsb ate0 selection of operation mode 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function lsck10 chip enable control of sck10 pin 0 sck10 is used as port (p23) when csie10 = 0. sck10 is used for clock output when csie10 = 1. 1 sck10 is fixed to high-level output when csie10 = 0. sck10 is used for clock output when csie10 = 1. scl101 scl100 selection of serial clock (f sck ) 0 0 external clock input to sck10 pin 01f x /2 2 (1.25 mhz) 10f x /2 3 (625 khz) 11f x /2 4 (313 khz) note when csie10 = 0 (sio1a0 operation stop status), the sck10/p23, so10/p24, and si10/p25 pins can freely be used as port pins. also, when csie10 is used for transmission only, the si10/p25 pin can be used as p25 (cmos i/o) (set bit 7 (re0) of adtc0 to 0). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 222 (2) automatic data transmit/receive control register 0 (adtc0) this register sets automatic reception enable/disable, the operation mode, and displays the state of automatic transmit/receive control. adtc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 12-3. format of automatic data transmit/receive control register 0 symbol <7> <6> 5 4 <3> 2 1 0 address after reset r/w adtc0 re0 arld0 0 0 trf0 0 0 0 ff79h 00h r/w note 1 re0 control of reception of automatic transmit/receive function 0 reception disabled note 2 1 reception enabled arld0 selection of operation mode for automatic transmit/receive function 0 one-shot mode 1 repeat mode trf0 status of automatic transmission/reception function note 3 0 detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic transmission/reception or when arld0 = 0) 1 automatic transmission/reception in progress (this bit is set to 1 when data is written to sio1a0) notes 1. bit 3 (trf0) is read-only. 2. when re0 is reset to 0, p25 (cmos i/o) is used even when bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) is set to 1. 3. use trf0, instead of csiif10 (interrupt request flag), to identify the completion of automatic transmission/reception. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 223 (3) automatic data transmit/receive interval specification register 0 (adti0) this register sets the automatic data transmit/receive function data transfer interval. adti0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 12-4. format of automatic data transmit/receive interval specification register 0 (1/2) symbol <7> 6 5 <4> <3> <2> <1> <0> address after reset r/w adti0 adti07 0 0 adti04 adti03 adti02 adti01 adti00 ff7bh 00h r/w adti07 data transfer interval control 0 no control of interval by adti0 to adti4 note 1 1 control of interval by adti0 to adti4 adti04 adti03 adti02 adti01 adti00 data transfer interval specification (f x = 5.0 mhz, f sck = 1.25 mhz) note 2 n 00000 0 00001 1.60 s + 0.5/f sck 1 0 0 0 1 0 2.40 s + 0.5/f sck 2 0 0 0 1 1 3.20 s + 0.5/f sck 3 0 0 1 0 0 4.00 s + 0.5/f sck 4 0 0 1 0 1 4.80 s + 0.5/f sck 5 0 0 1 1 0 5.60 s + 0.5/f sck 6 0 0 1 1 1 6.40 s + 0.5/f sck 7 0 1 0 0 0 7.20 s + 0.5/f sck 8 0 1 0 0 1 8.00 s + 0.5/f sck 9 0 1 0 1 0 8.80 s + 0.5/f sck 10 0 1 0 1 1 9.60 s + 0.5/f sck 11 0 1 1 0 0 10.4 s + 0.5/f sck 12 0 1 1 0 1 11.2 s + 0.5/f sck 13 0 1 1 1 0 12.0 s + 0.5/f sck 14 0 1 1 1 1 12.8 s + 0.5/f sck 15 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 224 figure 12-4. format of automatic data transmit/receive interval specification register 0 (2/2) symbol <7> 6 5 <4> <3> <2> <1> <0> address after reset r/w adti0 adti07 0 0 adti04 adti03 adti02 adti01 adti00 ff7bh 00h r/w adti04 adti03 adti02 adti01 adti00 data transfer interval specification (f x = 5.0 mhz, f sck = 1.25 mhz) note 2 n 1 0 0 0 0 13.6 s + 0.5/f sck 16 1 0 0 0 1 14.4 s + 0.5/f sck 17 1 0 0 1 0 15.2 s + 0.5/f sck 18 1 0 0 1 1 16.0 s + 0.5/f sck 19 1 0 1 0 0 16.8 s + 0.5/f sck 20 1 0 1 0 1 17.6 s + 0.5/f sck 21 1 0 1 1 0 18.4 s + 0.5/f sck 22 1 0 1 1 1 19.2 s + 0.5/f sck 23 1 1 0 0 0 20.0 s + 0.5/f sck 24 1 1 0 0 1 20.8 s + 0.5/f s ck 25 1 1 0 1 0 21.6 s + 0.5/f sck 26 1 1 0 1 1 22.4 s + 0.5/f sck 27 1 1 1 0 0 23.2 s + 0.5/f sck 28 1 1 1 0 1 24.0 s + 0.5/f sck 29 1 1 1 1 0 24.8 s + 0.5/f sck 30 1 1 1 1 1 25.6 s + 0.5/f sck 31 notes 1. the interval time depends only on the cpu processing. 2. the data transfer interval time is found from the following expressions (n: value set to adti00 to adti04). <1> n = 0 interval time = + <2> n = 1 to 31 interval time = + cautions 1. do not write to adti0 during operation of the automatic transmit/receive function. 2. be sure to set bits 5 and 6 to 0. remark f x : main system clock oscillation frequency f sck : serial clock frequency 2 f sck 0.5 f sck n+1 f sck 0.5 f sck www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 225 12.4 serial interface 1a0 operation serial interface 1a0 provides the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 12.4.1 operation stop mode in operation stop mode, serial transfer is not executed, thereby reducing the power consumption. the p23/sck10, p24/so10, and p25/si10 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 1a0 (csim1a0). (a) serial operation mode register 1a0 (csim1a0) csim1a0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1a0 to 00h. symbol <7> 6 <5> <4> 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operation serial counter port note 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function note when csie10 = 0 (sio1a0 operation stop status), the sck10/p23, so10/p24, and si10/p25 pins can freely be used as port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 226 12.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. communication is performed using three lines: a serial clock (sck10), serial output (so10), and serial input (si10). (1) register setting 3-wire serial i/o mode settings are performed using serial operation mode register 1a0 (csim1a0). (a) serial operation mode register 1a0 (csim1a0) csim1a0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1a0 to 00h. caution set the port mode register (pm ) in the 3-wire serial i/o mode as follows. set the output latch to 0. in the case of serial clock output (master transmission or master reception) set the sck10/p23 pin to output mode (pm23 = 0). in the case of serial clock input (slave transmission or slave reception) set the sck10/p23 pin to input mode (pm23 = 1). in transmission or transmission/reception mode set the so10/p24 pin to output mode (pm24 = 0). set the si10/p25 pin to input mode (pm25 = 1). in reception mode set the si10/p25 pin to input mode (pm25 = 1). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 227 symbol <7> 6 <5> <4> 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operation serial counter port note 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function dir10 specification of first bit of serial transfer data 0msb 1lsb ate0 selection of operation mode 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function lsck10 chip enable control of sck10 pin 0 sck10 is used as port (p23) when csie10 = 0. sck10 is used for clock output when csie10 = 1. 1 sck10 is fixed to high-level output when csie10 = 0. sck10 is used for clock output when csie10 = 1. scl101 scl100 selection of serial clock 0 0 external clock input to sck10 pin 01f x /2 2 (1.25 mhz) 10f x /2 3 (625 khz) 11f x /2 4 (313 khz) note when csie10 = 0 (sio1a0 operation stop status), the sck10/p23, so10/p24, and si10/p25 pins can freely be used as port pins. also, when csie10 is used for transmission only, the si10/p25 pin can be used as p25 (cmos i/o) (set bit 7 (re0) of adtc0 to 0). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 228 (2) communication operation in 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in synchronization with the serial clock. serial i/o shift register 1a0 (sio1a0) shift operations are performed in synchronization with the fall of the serial clock (sck10). then transmit data is held in the so10 latch and output from the so10 pin. also, receive data input to the si10 pin is latched in the sio1a0 on the rise of sck10. at the end of an 8-bit transfer, the operation of sio1a0 stops automatically, and the interrupt request signal (intcsi10) is generated. figure 12-5. 3-wire serial i/o mode timing (1/2) (i) master operation timing 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck10 so10 note si10 sio1a0 write intcsi10 note the value of the last bit previously output is output. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 229 figure 12-5. 3-wire serial i/o mode timing (2/2) (ii) slave operation timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck10 si10 note so10 sio1a0 write intcsi10 note the value of the last bit previously output is output. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 230 (3) msb/lsb switching as the start bit in the 3-wire serial i/o mode, transfer can be selected to start from the msb or lsb. figure 12-6 shows the configuration of serial i/o shift register 1a0 (sio1a0) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 6 (dir10) of serial operation mode register 1a0 (csim1a0). figure 12-6. circuit of switching in transfer bit order 7 6 internal bus 1 0 lsb-first msb-first read/write gate si10 shift i/o shift register 1a0 (sio1a0) read/write gate so10 sck10 dq so1 latch start bit switching is realized by switching the bit order for data write to sio1a0. the sio1a0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (4) transfer start serial transfer is started by setting transfer data to serial i/o shift register 1a0 (sio1a0) when the following two conditions are satisfied. ? bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) = 1 ? internal serial clock is stopped or sck10 is high after 8-bit serial transfer. caution if csie10 is set to ? 1 ? after data is written to sio1a0, transfer does not start. termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (intcsi10). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 231 12.4.3 3-wire serial i/o mode with automatic transmit/receive function this 3-wire serial i/o mode is used for transmission/reception of a maximum of 16-byte data without the use of software. once transfer is started, the set number of bytes of the data prestored in the ram can be transmitted, and the set number of bytes of data can be received and stored in the ram. (1) register setting the 3-wire serial i/o mode with automatic transmit/receive function is set with serial operation mode register 1a0 (csim1a0), automatic data transmit/receive control register 0 (adtc0) and automatic data transmit/receive interval specification register 0 (adti0). (a) serial operation mode register 1a0 (csim1a0) csim1a0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1a0 to 00h. caution set the port mode register (pm ) in the 3-wire serial i/o mode with automatic transmit/ receive function as follows. set the output latch to 0. in the case of serial clock output (master transmission or master reception) set the sck10/p23 pin to output mode (pm23 = 0). in the case of serial clock input (slave transmission or slave reception) set the sck10/p23 pin to input mode (pm23 = 1). in transmission or transmission/reception mode set the so10/p24 pin to output mode (pm24 = 0). set the si10/p25 pin to input mode (pm25 = 1). in reception mode set the si10/p25 pin to input mode (pm25 = 1). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 232 symbol <7> 6 <5> <4> 3 2 1 0 address after reset r/w csim1a0 csie10 dir10 ate0 lsck10 0 0 scl101 scl100 ff78h 00h r/w specification of operation enable/disable csie10 shift register operation serial counter port note 0 operation stopped cleared port function 1 operation enabled count operation enabled serial function + port function dir10 specification of first bit of serial transfer data 0msb 1lsb ate0 selection of operation mode 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function lsck10 chip enable control of sck10 pin 0 sck10 is used as port (p23) when csie10 = 0. sck10 is used for clock output when csie10 = 1. 1 sck10 is fixed to high-level output when csie10 = 0. sck10 is used for clock output when csie10 = 1. scl101 scl100 selection of serial clock 0 0 external clock input to sck10 pin 01f x /2 2 (1.25 mhz) 10f x /2 3 (625 khz) 11f x /2 4 (313 khz) note when csie10 = 0 (sio1a0 operation stop status), the sck10/p23, so10/p24, and si10/p25 pins can freely be used as port pins. also, when csie10 is used for transmission only, the si10/p25 pin can be used as p25 (cmos i/o) (set bit 7 (re0) of adtc0 to 0). remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 233 (b) automatic data transmit/receive control register 0 (adtc0) adtc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. symbol <7> <6> 5 4 <3> 2 1 0 address after reset r/w adtc0 re0 arld0 0 0 trf0 0 0 0 ff79h 00h r/w note 1 re0 control of reception of automatic transmit/receive function 0 reception disabled note 2 1 reception enabled arld0 selection of operation mode for automatic transmit/receive function 0 one-shot mode 1 repeat mode trf0 status of automatic transmit/receive function note 3 0 detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic transmission/reception or when arld0 = 0) 1 automatic transmission/reception in progress (this bit is set to 1 when data is written to sio1a0) notes 1. bit 3 (trf0) is read-only. 2. when re0 is reset to 0, p25 (cmos i/o) is used even when bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) is set to 1. 3. use trf0, instead of csiif10 (interrupt request flag), to identify the completion of automatic transmission/reception. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 234 (c) automatic data transmit/receive interval specification register 0 (adti0) adti0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. symbol <7> 6 5 <4> <3> <2> <1> <0> address after reset r/w adti0 adti07 0 0 adti04 adti03 adti02 adti01 adti00 ff7bh 00h r/w adti07 data transfer interval control 0 no control of interval by adti0 to adti4 note 1 1 control of interval by adti0 to adti4 adti04 adti03 adti02 adti01 adti00 data transfer interval specification (f x = 5.0 mhz, f sck = 1.25 mhz) note 2 n 00000 0 00001 1.60 s + 0.5/f sck 1 0 0 0 1 0 2.40 s + 0.5/f sck 2 0 0 0 1 1 3.20 s + 0.5/f sck 3 0 0 1 0 0 4.00 s + 0.5/f sck 4 0 0 1 0 1 4.80 s + 0.5/f sck 5 0 0 1 1 0 5.60 s + 0.5/f sck 6 0 0 1 1 1 6.40 s + 0.5/f sck 7 0 1 0 0 0 7.20 s + 0.5/f sck 8 0 1 0 0 1 8.00 s + 0.5/f sck 9 0 1 0 1 0 8.80 s + 0.5/f sck 10 0 1 0 1 1 9.60 s + 0.5/f sck 11 0 1 1 0 0 10.4 s + 0.5/f sck 12 0 1 1 0 1 11.2 s + 0.5/f sck 13 0 1 1 1 0 12.0 s + 0.5/f sck 14 0 1 1 1 1 12.8 s + 0.5/f sck 15 (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 235 symbol <7> 6 5 <4> <3> <2> <1> <0> address after reset r/w adti0 adti07 0 0 adti04 adti03 adti02 adti01 adti00 ff7bh 00h r/w adti04 adti03 adti02 adti01 adti00 data transfer interval specification (f x = 5.0 mhz, f sck = 1.25 mhz) note 2 n 1 0 0 0 0 13.6 s + 0.5/f sck 16 1 0 0 0 1 14.4 s + 0.5/f sck 17 1 0 0 1 0 15.2 s + 0.5/f sck 18 1 0 0 1 1 16.0 s + 0.5/f sck 19 1 0 1 0 0 16.8 s + 0.5/f sck 20 1 0 1 0 1 17.6 s + 0.5/f sck 21 1 0 1 1 0 18.4 s + 0.5/f sck 22 1 0 1 1 1 19.2 s + 0.5/f sck 23 1 1 0 0 0 20.0 s + 0.5/f sck 24 1 1 0 0 1 20.8 s + 0.5/f s ck 25 1 1 0 1 0 21.6 s + 0.5/f sck 26 1 1 0 1 1 22.4 s + 0.5/f sck 27 1 1 1 0 0 23.2 s + 0.5/f sck 28 1 1 1 0 1 24.0 s + 0.5/f sck 29 1 1 1 1 0 24.8 s + 0.5/f sck 30 1 1 1 1 1 25.6 s + 0.5/f sck 31 notes 1. the interval time depends only on the cpu processing. 2. the data transfer interval time is found from the following expressions (n: value set to adti00 to adti04). <1> n = 0 interval time = + <2> n = 1 to 31 interval time = + cautions 1. do not write to adti0 during operation of the automatic transmit/receive function. 2. be sure to set bits 5 and 6 to 0. remark f x : main system clock oscillation frequency f sck : serial clock frequency 2 f sck 0.5 f sck n+1 f sck 0.5 f sck www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 236 (2) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address ffa0h of buffer ram (up to ffafh). the transmit data should be in the order from higher address to lower address. <2> set the value obtained by subtracting 1 from the number of transmit data bytes to automatic data transmit/receive address pointer 0 (adtp0). (b) automatic transmit/receive mode setting <1> set bit 7 (csie10) and bit 5 (ate0) of serial operation mode register 1a0 (csim1a0) to 1. <2> set bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) to 1. <3> set the data transmit/receive interval in automatic data transmit/receive interval specification register 0 (adti0). <4> write any value to serial i/o shift register 1a0 (sio1a0) (transfer start trigger). caution writing any value to sio1a0 orders the start of automatic transmission/reception operation; the written value has no meaning. the following operations are automatically carried out when (a) and (b) are carried out. ? after the buffer ram data specified by adtp0 is transferred to sio1a0, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address specified by adtp0. ? adtp0 is decremented and the next data transmission/reception is carried out. data transmission/reception continues until the adtp0 decremental output becomes 00h and address ffa0h data is output (end of automatic transmission/reception). ? when automatic transmission/reception is terminated, bit 3 (trf0) of adtc0 is cleared to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 237 (3) communication operation (a) basic transmit/receive mode this transmit/receive mode is the same as the 3-wire serial i/o mode in which the specified number of data are transmitted/received in 8-bit units. serial transfer is started when any data is written to serial i/o shift register 1a0 (sio1a0) while bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) is set to 1. upon completion of transmission of the last byte, the interrupt request flag (csiif10) is set. the termination of automatic transmission/reception should be checked by using bit 3 (trf0) of automatic data transmit/receive control register 0 (adtc0), not by csiif10 because csiif10 of the interrupt request flag is cleared if an interrupt is acknowledged. figure 12-7 shows the basic transmit/receive mode operation timing, and figure 12-8 shows the operation flowchart. figure 12-9 shows buffer ram operation at 6-byte transmission. figure 12-7. basic transmit/receive mode operation timing sck10 so10 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif10 trf0 si10 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in the basic transmit/receive mode, the automatic transmit/receive function writes/reads data to/from the buffer ram after 1-byte transmission/reception, an interval is inserted till the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the maximum interval is dependent upon cpu processing and the value of automatic data transmit/receive interval specification register 0 (adti0) (refer to 12.4.3 (5) interval time of automatic transmission/reception). 2. when trf0 is cleared, the so10 pin becomes low level. remark csiif10: interrupt request flag trf0: bit 3 of automatic data transmit/receive control register 0 (adtc0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 238 figure 12-8. basic transmit/receive mode flowchart start write transmit data in buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti0 write any data to sio1a0 (start trigger) write transmit data from buffer ram to sio1a0 transmission/reception operation write receive data from sio1a0 to buffer ram pointer value = 0 no trf0 = 0 no end yes yes decrement pointer value software execution hardware execution software execution remark adtp0: automatic data transmit/receive address pointer 0 adti0: automatic data transmit/receive interval specification register 0 sio1a0: serial i/o shift register 1a0 trf0: bit 3 of automatic data transmit/receive control register 0 (adtc0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 239 in 6-byte transmission/reception (bit 6 (arld0) and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) are 0 and 1, respectively) in basic transmit/receive mode, buffer ram operates as follows. (i) before transmission/reception (refer to figure 12-9 (a)) after any data has been written to sio1a0 (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1a0. when transmission of the first byte is completed, receive data 1 (r1) is transferred from sio1a0 to the buffer ram, and automatic data transmit/receive address pointer 0 (adtp0) is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1a0. (ii) 4th byte transmit/receive point (refer to figure 12-9 (b)) transmission/reception of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to sio1a0. when transmission of the fourth byte is completed, receive data 4 (r4) is transferred from sio1a0 to the buffer ram, and adtp0 is decremented. (iii) completion of transmission/reception (refer to figure 12-9 (c)) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sio1a0 to the buffer ram, and the interrupt request flag (csiif10) is set (intcsi10 generation). figure 12-9. buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (1/2) (a) before transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h receive data 1 (r1) sio1a0 0 csiif10 5 adtp0 _ 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 240 figure 12-9. buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (2/2) (b) 4th byte transmission/reception receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h receive data 4 (r4) sio1a0 0 csiif10 2 adtp0 _ 1 (c) completion of transmission/reception receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) receive data 4 (r4) receive data 5 (r5) receive data 6 (r6) ffafh ffa5h ffa0h sio1a0 1 csiif10 0 adtp0 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user?s manual u15400ej3v0ud 241 (b) basic transmit mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when any data is written to serial i/o shift register 1a0 (sio1a0) while bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) is set to 1, and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) is set to 0. upon completion of transmission of the last byte, the interrupt request flag (csiif10) is set. the termination of automatic transmission/reception should be checked by using bit 3 (trf0) of automatic data transmit/receive control register 0 (adtc0), not by csiif10. if a receive operation is not executed, the p25/si10 pin can be used as normal i/o port. figure 12-10 shows the basic transmit mode operation timing, and figure 12-11 shows the operation flowchart. figure 12-12 shows buffer ram operation when repeatedly transmit 6 bytes. figure 12-10. basic transmit mode operation timing sck10 so10 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif10 trf0 interval cautions 1. because, in the basic transmit mode, the automatic transmit/receive function reads data from the buffer ram after 1-byte transmission, an interval is inserted until the next transmission. as the buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon cpu processing and the value of automatic data transmit/receive interval specification register 0 (adti0) (refer to 12.4.3 (5) interval time of automatic transmission/reception). 2. when trf0 is cleared, the so10 pin becomes low level. remark csiif10: interrupt request flag trf0: bit 3 of automatic data transmit/receive control register 0 (adtc0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 242 figure 12-11. basic transmit mode flowchart start write transmit data in buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti0 write any data to sio1a0 (start trigger) write transmit data from buffer ram to sio1a0 transmission operation pointer value = 0 no trf0 = 0 no end yes yes decrement pointer value software execution hardware execution software execution remark adtp0: automatic data transmit/receive address pointer 0 adti0: automatic data transmit/receive interval specification register 0 sio1a0: serial i/o shift register 1a0 trf0: bit 3 of automatic data transmit/receive control register 0 (adtc0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 243 in 6-byte transmission (bit 6 (arld0) and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) are 0) in basic transmit mode, buffer ram operates as follows. (i) before transmission (refer to figure 12-12 (a)) after any data has been written to sio1a0 (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1a0. when transmission of the first byte is completed, adtp0 is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1a0. (ii) 4th byte transmission point (refer to figure 12-12 (b)) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to sio1a0. when transmission of the fourth byte is completed, adtp0 is decremented. (iii) completion of transmission/reception (refer to figure 12-12 (c)) when transmission of the sixth byte is completed, the interrupt request flag (csiif10) is set (intcsi10 generation). figure 12-12. buffer ram operation in 6-byte transmission (in basic transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h sio1a0 0 csiif10 5 adtp0 _ 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 244 figure 12-12. buffer ram operation in 6-byte transmission (in basic transmit mode) (2/2) (b) 4th byte transmission point transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h sio1a0 0 csiif10 5 adtp0 _ 1 (c) completion of transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h sio1a0 1 csiif10 0 adtp0 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 245 (c) repeat transmit mode in this mode, data stored in the buffer ram is transmitted repeatedly. serial transfer is started by writing any data to serial i/o shift register 1a0 (sio1a0) when bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) is set to 1, and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) is set to 0. unlike the basic transmission mode, after the last byte (data in address ffa0h) has been transmitted, the interrupt request flag (csiif10) is not set, the value at the time when the transmission was started is set in automatic data transmit/receive address pointer 0 (adtp0) again, and the buffer ram contents are transmitted again. when a reception operation is not performed, the p25/si10 pin can be used as a normal i/o port. the repeat transmit mode operation timing is shown in figure 12-13, and the operation flowchart in figure 12-14. figure 12-13. repeat transmit mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 sck10 so10 caution because, in the repeat transmit mode, a read is performed on the buffer ram after the transmission of one byte, the interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu operation and the value of automatic data transmit/receive interval specification register 0 (adti0) (refer to 12.4.3 (5) interval time of automatic transmission/reception). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 246 figure 12-14. repeat transmit mode flowchart start write transmit data in buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti0 write any data to sio1a0 (start trigger) write transmit data from buffer ram to sio1a0 transmission operation pointer value = 0 no yes decrement pointer value software execution hardware execution reset adtp0 remark adtp0: automatic data transmit/receive address pointer 0 adti0: automatic data transmit/receive interval specification register 0 sio1a0: serial i/o shift register 1a0 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 247 in 6-byte transmission (bit 6 (arld0) and bit 7 (re0) of automatic data transmit/receive control register 0 (adtc0) are 1 and 0, respectively) in repeat transmit mode, buffer ram operates as follows. (i) before transmission (refer to figure 12-15 (a)) after any data has been written to sio1a0 (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1a0. when transmission of the first byte is completed, adtp0 is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1a0. (ii) upon completion of transmission of 6 bytes (refer to figure 12-15 (b)) when transmission of the sixth byte is completed, the interrupt request flag (csiif10) is not set. the previous pointer value is assigned to the adtp0. (iii) 7th byte transmission point (refer to figure 12-15 (c)) transmit data 1 (t1) is transferred from the buffer ram to sio1a0 again. when transmission of the first byte is completed, adtp0 is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1a0. figure 12-15. buffer ram operation in 6-byte transmission (in repeat transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h sio1a0 0 csiif10 5 adtp0 _ 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 248 figure 12-15. buffer ram operation in 6-byte transmission (in repeat transmit mode) (2/2) (b) upon completion of transmission of 6 bytes transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h sio1a0 0 csiif10 0 adtp0 (c) 7th byte transmission point transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) ffafh ffa5h ffa0h sio1a0 0 csiif10 5 adtp0 _ 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user?s manual u15400ej3v0ud 249 (d) automatic transmission/reception suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 7 (csie10) of serial operation mode register 1a0 (csim1a0) to 0. during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (csie10) is set to 0. it is suspended upon completion of 8-bit data transfer. when suspended, bit 3 (trf0) of automatic data transmit/receive control register 0 (adtc0) is set to 0 after transfer of the 8th bit, and all the port pins used alternately as serial interface pins (p23/sck10, p24/so10, p25/si10) are set to the port mode. during restart of transmission/reception, the remaining data can be transferred by setting csie10 to 1 and writing any data to serial i/o shift register 1a0 (sio1a0). cautions 1. if the halt instruction is executed during automatic transmission/reception, transfer is suspended and the halt mode is set even if 8-bit data is being transferred. 2. when suspending automatic transmission/reception, do not change the operation mode to 3-wire serial mode while trf0 = 1. figure 12-16. automatic transmission/reception suspension and restart sck10 so10 d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 si10 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csie10 = 0 (suspended command) suspend restart command csie10 = 1, write to sio1a0 csie10: bit 7 of serial operation mode register 1a0 (csim1a0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 12 serial interface 1a0 user ? s manual u15400ej3v0ud 250 (4) timing of interrupt request signal generation the interrupt request signal is generated in synchronization with the timing shown in table 12-2. table 12-2. timing of interrupt request signal generation operation mode timing of interrupt request signal master mode 10th serial clock at end of transfer single mode slave mode 8th serial clock at end of transfer repeat transmit mode not generated (5) interval time of automatic transmission/reception because read/write to/from the buffer ram using the automatic transmit/receive function is performed asynchronously to the cpu processing, the interval time is dependent on the cpu processing of the timing of the eighth rising of the serial clock and the set value of automatic data transmit/receive interval specification register 0 (adti0). whether the interval time is dependent on adti0 is selected by setting bit 7 (adti07) of adti0. if adti07 is reset to 0, the interval time is 2/f sck . if adti07 is set to 1, whichever is greater of the interval time determined by the set contents of adti0 or the interval time (2/f sck ) determined by the cpu processing is selected. figure 12-17 shows the interval time of automatic transmission/reception. remark f sck : serial clock frequency figure 12-17. interval time of automatic transmission/reception interval sck10 d7 so10 si10 csiif10 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 the following expression must be satisfied to access the buffer ram. 1 transfer cycle + interval time read access + write access + cpu buffer ram access (time) in the case of a ? high-speed cpu & low-speed sck ? , the interval time is not necessary. in the case of a ? low-speed cpu & high-speed sck ? , the interval time is necessary. in this case, make sure that a sufficient interval time elapses, by using automatic data transmit/receive interval specification register 0 (adti0), so that the above expression is satisfied. www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 251 chapter 13 lcd controller/driver 13.1 lcd controller/driver functions the functions of the lcd controller/driver of the pd789478 subseries are as follows. (1) automatic output of segment and common signals based on automatic display data memory read (2) two different display modes: 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) 16 to 28 segment signal outputs (s0 to s15, s16 to s27 note ), 4 common signal outputs (com0 to com3) (5) operation with subsystem clock is possible note usable by mask option or port function register the maximum number of displayable pixels is shown in table 13-1 below. table 13-1. maximum number of display pixels bias method time division common signals used maximum number of segments maximum number of display pixels 3 com0 to com2 84 (28 segments 3 commons) note 1 1/3 4 com0 to com3 28 112 (28 segments 4 commons) note 2 notes 1. the lcd panel of the figure consists of 9 rows with 3 segments per row. 2. the lcd panel of the figure consists of 14 rows with 2 segments per row. 13.2 lcd controller/driver configuration the lcd controller/driver includes the following hardware. table 13-2. configuration of lcd controller/driver item configuration display outputs segment signals: 16 to 28 common signals: 4 (com0 to com3) control registers lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user?s manual u15400ej3v0ud 252 the correspondence with the lcd display ram is shown in figure 13-1 below. figure 13-1. correspondence with lcd display ram address bit segment 76543210 fa1bh 0000 s27 note fa1ah 0000 s26 note fa19h 0 0 0 0 s25 note fa18h 0 0 0 0 s24 note fa17h 0 0 0 0 s23 note fa16h 0 0 0 0 s22 note fa15h 0 0 0 0 s21 note fa14h 0 0 0 0 s20 note fa13h 0 0 0 0 s19 note fa12h 0 0 0 0 s18 note fa11h 0 0 0 0 s17 note fa10h 0 0 0 0 s16 note fa0fh 0000 s15 fa0eh 0000 s14 fa0dh 0000 s13 fa0ch 0000 s12 fa0bh 0000 s11 fa0ah 0000 s10 fa09h 0 0 0 0 s9 fa08h 0 0 0 0 s8 fa07h 0 0 0 0 s7 fa06h 0 0 0 0 s6 fa05h 0 0 0 0 s5 fa04h 0 0 0 0 s4 fa03h 0 0 0 0 s3 fa02h 0 0 0 0 s2 fa01h 0 0 0 0 s1 fa00h 0 0 0 0 s0 common com3 com2 com1 com0 note segments s16 to s27 are selected in 1-bit units via a mask option or port function register (segment output pin/port pin). remark bits 4 to 7 are fixed to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user?s manual u15400ej3v0ud 253 figure 13-2. lcd controller/driver block diagram lcdc03 lcdc02 lcdc01 lcdc00 2 2 f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lcdon0 v lc0 com0 com1 com2 com3 3210 3210 65 74 fa00h lcdon0 3210 3210 65 74 fa1bh lcdon0 s27 f x /2 5 f x /2 6 f x /2 7 f xt s0 f lcd 3210 3210 65 74 fa0fh lcdon0 s15 lcdcl lips0 v lc2 caph capl v lc1 3210 3210 65 74 fa10h lcdon0 s16 lcdm00 lcd clock control register 0 (lcdc0) lcd display mode register 0 (lcdm0) lcd clock selector selector prescaler lcd drive voltage controller segment voltage controller common voltage controller common driver ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ....... ......... . . . . . . . . . . . . . . . . . . segment driver segment driver segment driver segment driver selector selector selector selector selected by mask option or port function register display data memory internal bus timing controller www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 254 13.3 registers controlling lcd controller/driver the lcd controller/driver is controlled by the following two registers. lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) (1) lcd display mode register 0 (lcdm0) lcdm0 specifies whether to enable display. it also specifies the segment/common pin output and display mode. lcdm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdm0 to 00h. figure 13-3. format of lcd display mode register 0 note when the lcd display panel is not used, set lips0 to 0 to reduce power consumption. caution bits 1 to 3, 5, and 6 must be set to 0. lcdon0 0 0 lips0 0 0 0 lcdm00 lcdm0 symbol address after reset r/w ffb0h 00h r/w <7>65<4>3210 lcd controller/driver display mode selection lcdm00 0 1 4 3 lcd display enable/disable lcdon0 0 1 display off (all segment outputs are deselect signal outputs) display on segment pin/common pin output control note lips0 0 1 output ground level to segment/common pin output select level to segment pin and lcd waveform to common pin number of time slices bias mode 1/3 1/3 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user?s manual u15400ej3v0ud 255 (2) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined according to the lcd clock and number of time slices. lcdc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdc0 to 00h. figure 13-4. format of lcd clock control register 0 lcdc03 lcdc02 lcdc01 lcdc00 lcdc0 symbol address after reset r/w ffb2h 00h r/w 76543210 lcd source clock (f lcd ) selection note lcdc03 0 0 1 1 lcdc02 0 1 0 1 lcd clock (lcdcl) selection lcdc01 0 0 1 1 lcdc00 0 1 0 1 0000 f lcd /2 6 f lcd /2 7 f lcd /2 8 f lcd /2 9 f xt (32.768 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) note specify an lcd source clock (f lcd ) frequency of at least 32 khz. cautions 1. bits 4 to 7 must be set to 0. 2. before changing the lcdc0 setting, be sure to disable the display (lcdon0 = 0). remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. as an example, table 13-3 lists the frame frequencies used when f xt (32.768 khz) is supplied as the lcd source clock (f lcd ). table 13-3. frame frequencies (hz) lcd clock (lcdcl) frequency number of time slices f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) 3 21 43 85 171 4 16 32 64 128 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 256 13.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. <1> set the lcd clock using lcd clock control register 0 (lcdc0). <2> set the time slice using lcdm00 (bit 0 of lcd display mode register 0 (lcdm0)). <3> set lips0 (bit 4 of lcdm0) (lips0 = 1) and output the deselect potential. <4> start output corresponding to each data memory by setting lcdon0 (bit 7 of lcdm0) (lcdon0 = 1). 13.5 lcd display data memory the lcd display data memory is mapped at addresses fa00h to fa1bh. data in the lcd display data memory can be displayed on the lcd panel using the lcd controller/driver. figure 13-5 shows the relationship between the contents of the lcd display data memory and the segment/common outputs. that part of the display data memory which is not used for display can be used as ordinary ram. figure 13-5. relationship between lcd display data memory contents and segment/common outputs (when using s16 to s27) s27 fa1bh s26 fa1ah s25 fa19h fa18h s24 s2 fa02h s1 fa01h s0 fa00h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution no memory has been installed as the higher 4 bits of the lcd display data memory. be sure to set them to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 257 13.6 common and segment signals each pixel of the lcd panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (lcd drive voltage, v lcd ). it turns off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segment signals for an lcd panel would deteriorate it. to avoid this problem, this lcd panel is driven with ac voltage. (1) common signals each common signal is selected sequentially according to the specified number of time slices at the timing listed in table 13-4. this cycle of operation is performed repeatedly. in the three-time-slice mode, leave the com3 pin open. table 13-4. com signals com signal number of time slices com0 com1 com2 com3 three-time-slice mode open four-time-slice mode (2) segment signals the segment signals correspond to lcd display data memory. bits 0, 1, 2, and 3 of each byte are read in synchronization with com0, com1, com2, and com3, respectively. if the contents of each bit are 1, that bit is converted to the select voltage, and if 0, it is converted to the deselect voltage. the conversion results are output to the segment pins. check, with the information given above, what combination of the front-surface electrodes (corresponding to the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. bit 3 of the lcd display data memory is not used for lcd display in the three-time-slice mode. so this bit can be used for purposes other than display. lcd display data memory bits 4 to 7 are fixed to 0. (3) output waveforms of common and segment signals when both common and segment signals are at the select voltage, a display-on voltage of v lcd is obtained. the other combinations of the signals correspond to the display-off voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 258 figure 13-6 shows the common signal waveforms, and figure 13-7 shows the voltages and phases of the common and segment signals. figure 13-6. common signal waveforms t: one lcd clock period t f : frame frequency figure 13-7. voltages and phases of common and segment signals select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period comn (three-time-slice mode) t f = 3 t v lc0 v ss v lcd v lc1 v lc2 t f = 4 t comn (four-time-slice mode) v lc0 v lcd v lc1 v lc2 v ss www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 259 13.7 display modes 13.7.1 three-time-slice display example figure 13-9 shows how a nine-digit lcd panel having the display pattern shown in figure 13-8 is connected to the segment signals (s0 to s26) and the common signals (com0 to com2) of the pd789478 subseries chip. this example displays the data ? 123456.789 ? in the lcd panel. the contents of the display data memory (addresses fa00h to fa1ah) correspond to this display. the following description focuses on numeral ? 6. ? ( ) displayed as the fourth digit from the right. to display ? 6. ? in the lcd panel, it is necessary to apply the select or deselect voltage to the s9 to s11 pins according to table 13-5 at the timing of the common signals com0 to com2; see figure 13-8 for the relationship between the segment signals and lcd segments. table 13-5. select and deselect voltages (com0 to com2) segment common s9 s10 s11 com0 deselect select select com1 select select select com2 select select ? according to table 13-5, it is determined that the display data memory location (fa09h) that corresponds to s9 must contain x110. figure 13-10 shows an example of lcd drive waveforms between the s9 signal and each common signal. when the select voltage is applied to s9 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 13-8. three-time-slice lcd display pattern and electrode connections s 3n+2 s 3n com0 com2 s 3n+1 com1 remark n = 0 to 8 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 260 figure 13-9. example of connecting three-time-slice lcd panel x ? : can be used to store any data because there is no corresponding segment in the lcd panel. : can always be used to store any data because the three-time-slice mode is being used. timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 8 9 a s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 s 25 s 26 com 3 com 2 com 1 com 0 open 1 00101101110111011011111111 bit 0 001110011011011111001111011 bit 1 00 10 10 00 10 11 00 10 00 bit 2 x ? x ? x ? x ? x ? x ? x ? x ? x ? bit 3 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 261 figure 13-10. three-time-slice lcd drive waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0-s9 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 s9 v lc1 v ss +v lcd 0 com1-s9 ? v lcd +1/3v lcd ? 1/3v lcd +v lcd 0 com2-s9 ? v lcd +1/3v lcd ? 1/3v lcd t f www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user?s manual u15400ej3v0ud 262 13.7.2 four-time-slice display example figure 13-12 shows how a 14-digit lcd panel having the display pattern shown in figure 13-11 is connected to the segment signals (s0 to s27) and the common signals (com0 to com3) of the pd789478 subseries chip. this example displays the data ?123456.78901234? in the lcd panel. the contents of the display data memory (addresses fa00h to fa1bh) correspond to this display. the following description focuses on numeral ?6.? ( ) displayed as the ninth digit from the right. to display ?6.? in the lcd panel, it is necessary to apply the select or deselect voltage to the s16 and s17 pins according to table 13- 6 at the timing of the common signals com0 to com3; see figure 13-11 for the relationship between the segment signals and lcd segments. table 13-6. select and deselect voltages (com0 to com3) segment common s16 s17 com0 select select com1 deselect select com2 select select com3 select select according to table 13-6, it is determined that the display data memory location (fa10h) that corresponds to s16 must contain 1101. figure 13-13 shows examples of lcd drive waveforms between the s16 signal and each common signal. when the select voltage is applied to s16 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 13-11. four-time-slice lcd display pattern and electrode connections remark n = 0 to 13 com0 s 2n com1 s 2n+1 com2 com3 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 263 figure 13-12. example of connecting four-time-slice lcd panel 0 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 8 9 a b s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 s 25 s 26 s 27 com 3 com 2 com 1 com 0 0 000101101111111111110001011 bit 0 0 1 11111111010011111010111111 bit 1 1 011001010111011101110110010 bit 2 0 001010001011001000100010100 bit 3 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 264 figure 13-13. four-time-slice lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0-s16 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-s16 ? v lcd +1/3v lcd ? 1/3v lcd v lc0 v lc2 s16 v lc1 v ss remark the waveforms of com2-s16 and com3-s16 are not shown. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 13 lcd controller/driver user ? s manual u15400ej3v0ud 265 13.8 examples of lcd drive power connections since the pd789478 subseries employs a divider resistor system for generating lcd drive power, it requires external voltage divider resistors. figure 13-14 shows an example of lcd drive power connections. the lcd drive voltage is supplied to v lc0 , and 2/3 and 1/3 of v lc0 are supplied to the v lc1 and v lc0 pins, respectively. figure 13-14. example of lcd drive power connections figure 13-14 shows an example in which the current flow through voltage divider resistors is cut off by using p50 when the lcd is not used. the following explains this case. <1> set p50 to the output mode (pm50 = 0) <2> set the p50 output latch to 0, and output a low level from p50. the lcd drive voltage is supplied to v lc0 , v lc1 , and v lc2 . <3> set lcdon0 (bit 7 of lcdm0) to 1, and turn on the display. <1> clear lcdon0 (bit 7 of lcdm0) to 1, and turn off the display. <2> set the p50 output latch to 1, and output a high level from p50 (hi-z). when the display is off, the current flow between v dd and p50 is cut off by setting the p50 (n-ch open drain) output level to high impedance. v lc0 v lc1 v lc2 v dd p50 (n-ch o.d.) www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 266 chapter 14 multiplier 14.1 multiplier function the multiplier has the following function. ? calculation of 8 bits 8 bits = 16 bits 14.2 multiplier configuration (1) 16-bit multiplication result storage register 0 (mul0) this register stores the 16-bit result of multiplication. this register holds the result of multiplication after 16 cpu clocks have elapsed. mul0 is set with a 16-bit memory manipulation instruction. reset input makes this register undefined. caution although this register is manipulated with a 16-bit memory manipulation instruction, it can also be manipulated with an 8-bit memory manipulation instruction. when using an 8-bit memory manipulation instruction, however, access the register by means of direct addressing. (2) multiplication data registers a and b (mra0 and mrb0) these are 8-bit multiplication data storage registers. the multiplier multiplies the values of mra0 and mrb0. mra0 and mrb0 are set with an 8-bit memory manipulation instruction. reset input makes these registers undefined. figure 14-1 shows the block diagram of the multiplier. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 14 multiplier user?s manual u15400ej3v0ud 267 figure 14-1. block diagram of multiplier internal bus selector counter value 3 cpu clock start clear counter output 16-bit adder 16-bit multiplication result storage register 0 (master) (mul0) 16-bit multiplication result storage register 0 (slave) multiplication data register a (mra0) multiplication data register b (mrb0) internal bus 3-bit counter mulst0 reset multiplier control register 0 (mulc0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 14 multiplier user ? s manual u15400ej3v0ud 268 14.3 multiplier control register the multiplier is controlled by the following register. ? multiplier control register 0 (mulc0) (1) multiplier control register 0 (mulc0) mulc0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. mulc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 14-2. format of multiplier control register 0 caution be sure to set bits 1 to 7 to 0. mulst0 0 1 multiplier operation start control bit 0000000 mulst0 mulc0 symbol address after reset r/w ffd2h 00h r/w 7654321<0> stop operation after resetting counter to 0. enable operation operation stopped operation in progress operating status of multiplier www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 14 multiplier user ? s manual u15400ej3v0ud 269 14.4 multiplier operation the multiplier of the pd789478 subseries can execute the calculation of 8 bits 8 bits = 16 bits. figure 14-3 shows the operation timing of the multiplier where mra0 is set to aah and mrb0 is set to d3h. <1> counting is started by setting mulst0. <2> the data generated by the selector is added to the data of mul0 at each cpu clock, and the counter value is incremented by one. <3> if mulst0 is cleared when the counter value is 111b, the operation is stopped. at this time, mul0 holds the data. <4> while mulst0 is low, the counter and slave are cleared. figure 14-3. multiplier operation timing (example of aah d3h) aa d3 000b 00aa 0000 001b 010b 011b 100b 101b 110b 111b 000b 0154 0000 0000 0aa0 0000 2a80 5500 00aa 00aa 01fe 01fe 01fe 0c9e 0c9e 371e 8c1e 00aa 01fe 01fe 01fe 0c9e 0c9e 371e 0000 cpu clock mra0 mrb0 mulst0 counter selector output mul0 (master) (slave) www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 270 chapter 15 remote controller receiver 15.1 remote controller receiver functions the remote controller receiver uses the following remote controller modes. ? type a reception mode ? guide pulse (half clock) provided 15.2 remote controller receiver configuration the remote controller receiver includes the following hardware. table 15-1. remote controller receiver configuration item configuration registers remote controller receive shift register (rmsr) remote controller receive data register (rmdr) remote controller shift register receive counter register (rmscr) remote controller receive gphs compare register (rmgphs) remote controller receive gphl compare register (rmgphl) remote controller receive dls compare register (rmdls) remote controller receive dll compare register (rmdll) remote controller receive dh0s compare register (rmdh0s) remote controller receive dh0l compare register (rmdh0l) remote controller receive dh1s compare register (rmdh1s) remote controller receive dh1l compare register (rmdh1l) remote controller receive end width select register (rmer) control register remote controller receive control register (rmcn) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user?s manual u15400ej3v0ud 271 figure 15-1. block diagram of remote controller receiver (1) remote controller receive shift register (rmsr) this is an 8-bit register for reception of remote controller data. data is stored in bit 7 first. each time new data is stored, the stored data is shifted to the lower bits. therefore, the latest data is stored in bit 7, and the first data is stored in bit 0. rmsr is read with an 8-bit memory manipulation instruction. reset input sets rmsr to 00h. also, rmsr is cleared to 00h under any of the following conditions. ? remote controller stops operation (rmen = 0). ? error is detected (intrerr is generated). ? intdfull is generated. ? rmsr is read after intrend has been generated. caution reading rmsr is disabled during remote controller reception. complete reception, then read rmsr. when the reading operation is complete, rmsr is cleared. therefore, values once read are not guaranteed. rin/p34 noise canceler f x /2 6 f x /2 7 f x /2 8 f xt clock counter selector remote controller receive control register ( rmcn) internal bus rmin prsen rmck1 rmck0 input control edge detection compare register rmgphs rmgphl rmdls rmdll rmdh0s rmdh0l rmdh1s rmdh1l ncw rmen register selection comparator data detection selection control signal remote controller shift register receive counter register (rmscr) intdfull remote controller receive shift register (rmsr) remote controller receive data register (rmdr) intrerr intrend intgp intrin rmin rmen ncw end-width select register (rmer) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 272 (2) remote controller receive data register (rmdr) this register holds the remote controller reception data. when the remote controller receive shift register (rmsr) overflows, the data in rmsr is transferred to rmdr. bit 7 stores the last data, and bit 0 stores the first data. intdfull is generated at the same time as data is transferred from rmsr to rmdr. rmdr is read with an 8-bit memory manipulation instruction. reset input sets rmdr to 00h. when the remote controller operation is disabled (rmen = 0), rmsr is cleared to 00h. caution when intdfull has been generated, read rmdr before the next 8-bit data is received. if the next intdfull is generated before the read operation is complete, rmdr is overwritten. (3) remote controller shift register receive counter register (rmscr) this is an 8-bit counter register used to indicate the number of valid bits remaining in the remote controller receive shift register (rmsr) when remote controller reception is complete (intrend is generated). reading the values of this register allows confirmation of the number of bits, even if the received data is in a format other than an integral multiple of 8 bits. rmscr is read with an 8-bit memory manipulation instruction. reset input sets rmscr to 00h. it is cleared to 00h under any of the following conditions. ? remote controller stops operation (rmen = 0). ? error is detected (intrerr is generated). ? rmsr is read after intrend has been generated. caution when intrend has been generated, immediately read rmscr before reading rmsr. if reading occurs at another timing, the value is not guaranteed. figure 15-2. operation examples of rmsr, rmscr, and rmdr registers when receiving 1010101011111111b (16 bits) rmsr 76543210 rmscr rmdr after reset 0 0 0 0 0 0 0 0 00h 00000000b receiving 1 bit 1 0 0 0 0 0 0 0 01h 00000000b receiving 2 bits 0 1 0 0 0 0 0 0 02h 00000000b receiving 3 bits 1 0 1 0 0 0 0 0 03h 00000000b ? ???????? ? ? receiving 7 bits 1 0 1 0 1 0 1 0 07h 00000000b receiving 8 bits rmdr transfer 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 00h 00h 00000000b 01010101b receiving 9 bits 1 0 0 0 0 0 0 0 01h 01010101b receiving 10 bits 1 1 0 0 0 0 0 0 02h 01010101b ? ???????? ? ? receiving 16 bits rmdr transfer 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 00h 00h 01010101b 11111111b www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 273 (4) remote controller receive gphs compare register (rmgphs) this register is used to detect the high level of a remote controller guide pulse (short side). rmgphs is set with an 8-bit memory manipulation instruction. reset input sets rmgphs to 00h. (5) remote controller receive gphl compare register (rmgphl) this register is used to detect the high level of a remote controller guide pulse (long side). rmgphl is set with an 8-bit memory manipulation instruction. reset input sets rmgphl to 00h. (6) remote controller dls compare register (rmdls) this register is used to detect the low level of a remote controller data (short side). rmdls is set with an 8-bit memory manipulation instruction. reset input sets rmdls to 00h. (7) remote controller receive dll compare register (rmdll) this register is used to detect the low level of a remote controller data (long side). rmdll is set with an 8-bit memory manipulation instruction. reset input sets rmdll to 00h. rin allowable range counter value rmgphs register value rmgphl register value guide pulse if rmgphs counter value < rmgphl is satisfied, it is assumed that the high level of the guide pulse has been successfully received. rin counter value rmdls register value rmdll register value data 0 allowable range if rmdls counter value < rmdll is satisfied, it is assumed that the low level of data 0 or data 1 has been successfully received. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 274 (8) remote controller receive dh0s compare register (rmdh0s) this register is used to detect the high level of remote controller data 0 (short side). rmdh0s is set with an 8-bit memory manipulation instruction. reset input sets rmdh0s to 00h. (9) remote controller receive dh0l compare register (rmdh0l) this register is used to detect the high level of remote controller data 0 (long side). rmdh0l is set with an 8-bit memory manipulation instruction. reset input sets rmdh0l to 00h. (10) remote controller receive dh1s compare register (rmdh1s) this register is used to detect the high level of remote controller data 1 (short side). rmdh1s is set with an 8-bit memory manipulation instruction. reset input sets rmdh1s to 00h. (11) remote controller receive dh1l compare register (rmdh1l) this register is used to detect the high level of remote controller data 1 (long side). rmdh1l is set with an 8-bit memory manipulation instruction. reset input sets rmdh1l to 00h. rin allowable range counter value rmdh0s register value rmdh0l register value data 0 if rmdh0s counter value < rmdh0l is satisfied, it is assumed that the high level of data 0 has been successfully received, and therefore rmsr receives the data. rin allowable range counter value rmdh1s register value rmdh1l register value data 1 if rmdh1s counter value < rmdh1l is satisfied, it is assumed that the high level of data 1 has been successfully received, and therefore rmsr receives the data. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 275 (12) remote controller receive end-width select register (rmer) this register determines the interval between the timing at which the intrend signal is output. rmer is set with an 8-bit memory manipulation instruction. reset input sets rmer to 00h. rin counter value = rmer data rmdll intrend counter caution for rmer and all the remote controller receive compare registers (rmgphs, rmgphl, rmdls, rmdll, rmdh0s, rmdh0l, rmdh1s, and rmdh1l), disable remote controller reception (bit 7 (rmen) of the remote controller receive control register (rmcn) = = = = 0) first, and then change the value. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 276 15.3 registers to control remote controller receiver the remote controller receiver is controlled by the following register. ? remote controller receive control register (rmcn) (1) remote controller receive control register (rmcn) this register is used to enable/disable remote controller reception and to set the noise elimination width, clock internal division, input invert signal, and source clock. rmcn is set with an 8-bit memory manipulation instruction. reset input sets rmcn to 00h. figure 15-3. format of remote controller receive control register (1/2) symbol76543210addressafter resetr/w rmcn rmen ncw prsen rmin 0 0 rmck1 rmck0 ff60h 00h r/w rmen control of remote controller receive operation 0 disable remote controller reception 1 enable remote controller reception ncw noise elimination width control signal 0 eliminate noise less than 1/f prs 1 eliminate noise less than 2/f prs prsen internal clock division control signal 0 clock not divided internally (f prs = f rem ) 1 clock internally divided into two (f prs = f rem /2) rmin remote controller input invert signal 0 input positive phase 1 input negative phase cautions 1. always set bits 2 and 3 to 0. 2. to change the values of ncw, prsen, rmin, rmck1, and rmck0, disable remote controller reception (rmen = 0) first. remarks 1. f rem : source clock of remote controller counter (selected by bits 0 and 1 (rmck0 and rmck1) 2. f prs : operation clock inside remote controller receiver www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 277 figure 15-3. format of remote controller receive control register (2/2) symbol76543210addressafter resetr/w rmcn rmen ncw prsen rmin 0 0 rmck1 rmck0 ff60h 00h r/w rmck1 rmck0 selection of source clock (f rem ) of remote controller counter 00f x /2 6 (625 khz) 01f x /2 7 (313 khz) 10f x /2 8 (156 khz) 11f xt (32.768 khz) cautions 1. always set bits 2 and 3 to 0. 2. to change the values of ncw, prsen, rmin, rmck1, and rmck0, disable remote controller reception (rmen = = = = 0) first. remarks 1. f x : oscillation frequency of main system clock 2. f xt : oscillation frequency of subsystem clock 3. the parenthesized values apply to operation at f x = 4.0 mhz and f xt = 32.768 khz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 278 15.4 operation of remote controller receiver the following remote controller reception mode is used for this remote controller receiver. ? type a reception mode with guide pulse (half clock) 15.4.1 format of type a reception mode figure 15-4 shows the data format for type a. figure 15-4. example of type a data format rin intdfull guide pulse intgp rmer data ? 0 ? data ? 1 ? 0.6 ms 1.8 ms 1.2 ms 2.4 ms intrin intrend rmdll data ? 1 ? data ? 0 ? data ? 0 ? data ? 0 ? data ? 0 ? data ? 0 ? data ? 0 ? 15.4.2 operation flow of type a reception mode figure 15-5 shows the operation flow. cautions 1. when intrerr is generated, rmsr and rmscr are automatically cleared immediately. 2. when data has been set to all the bits of rmsr, the following processing is automatically performed. ? ? ? ? the value of rmsr is transferred to rmdr. ? ? ? ? intdfull is generated. ? ? ? ? rmsr is cleared. rmdr must then be read before the next data is set to all the bits of rmsr. 3. when intrend has been generated, read rmscr first followed by rmsr. when rmsr has been read, rmscr and rmsr are automatically cleared. if intrend is generated, the next data cannot be received until rmsr is read. 4. rmsr, rmscr, and rmdr are cleared simultaneously to operation termination (rmen = = = = 0). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 279 figure 15-5. operation flow of type a reception mode note read rmdr before data has been set to all the bits of rmsr. longer than end interval? no yes start yes no generate intgp set data to all bits of rmsr ok? no guide pulse high level width ok? data low level width ok? generate intrend read rmscr process received data receive operation completed yes data high level width ok? set data to rmsr end no no yes yes yes generate intrerr no yes clear rmsr and rmscr clear rmsr, rmscr, and rmdr rmsr rmdr generate intdfull clear rmsr read rmsr clear rmsr and rmscr : software processing (user executes via program) : hardware processing (macro automatically performs) read rmdr note set compare registers operation enabled ( rmen = 1) terminate operation ( rmen = 0) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 280 15.4.3 timing operation varies depending on the positions of the pin input waveform below. (1) guide pulse high level width determination relationship between rmgphs/rmgphl/counter position of waveform corresponding operation counter < pmgphs <1>: short measuring guide pulse high-level width is started from the next rising edge. pmgphs counter < pmgphl <2>: within the range intgp is generated. data measurement is started. pmgphl counter <3>: long measuring guide pulse high-level width is started from the next rising edge. (2) data low level width determination relationship between rmdls/rmdll/counter position of waveform corresponding operation counter < rmdls <1>: short error interrupt intrerr is generated. measuring guide pulse high-level width is started. rmdls counter < rmdll <2>: within the range measuring data high-level width is started. rmdll counter <3>: long measuring the end width is started from the ? point. rin rmgphs rmgphl allowable range <1> <2> <3> rin rin rin rmdls rmdll allowable range <1> <2> <3> rin rin ? www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 281 (3) data high level width determination relationship between rmdh0s/rmdh0l/rmdh1s/rmdh1l/counter position of waveform corresponding operation counter < rmdh0s <1>: short error interrupt intrerr is generated. measuring the guide pulse high-level width is started at the next rising edge. rmdh0s counter < rmdh0l <2>: within the range data 0 is received. measuring data low-level width is started. rmdh0l counter < rmdh1s <3>: outside of the range error interrupt intrerr is generated. measuring the guide pulse high-level width is started at the next rising edge. rmdh1s counter < rmdh1l <4>: within the range data 1 is received. measuring the data low-level width is started. rmdh1l counter <5>: long error interrupt intrerr is generated at the ? point. measuring the guide pulse high-level width is started at the next rising edge. rin rmdh0s rmdh0l allowable range <1> <2> <3> rin rin rmdh1s rmdh1l rin rin <5> <4> allowable range ? www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 282 (4) end width determination rin rmdls rmdll <1> <2> rin rmer ? relationship between rmer/counter position of waveform corresponding operation counter < rmer <1>: short error interrupt intrerr is generated. measuring the guide pulse high-level width is started. rmer counter <2>: long intrend is generated at the ? point. reception via circuit stops until rmsr is read. 15.4.4 compare register setting this remote controller receiver has the following 9 types of compare registers. ? remote controller receive gphs compare register (rmgphs) ? remote controller receive gphl compare register (rmgphl) ? remote controller receive dls compare register (rmdls) ? remote controller receive dll compare register (rmdll) ? remote controller receive dh0s compare register (rmdh0s) ? remote controller receive dh0l compare register (rmdh0l) ? remote controller receive dh1s compare register (rmdh1s) ? remote controller receive dh1l compare register (rmdh1l) ? remote controller receive end width select register (rmer) use formulas (1) to (3) below to set the value of each compare register. making allowances for tolerance enables a normal reception operation, even if the rin input waveform is rin_1 or rin_2 shown in figure 15-6 due to the effect of noise. cautions 1. always set each compare register while remote controller reception is disabled (rmen = = = = 0). 2. set the set values so that they satisfy all the following three conditions. ? ? ? ? rmgphs < < < < rmgphl ? ? ? ? rmdls < < < < rmdll ? ? ? ? rmdh0s < < < < rmdh0l rmdh1s < < < < rmdh1l www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 283 figure 15-6. setting example (where n1 = = = = 1, n2 = = = = 2) rin rin_2 t w rin_1 clock rmgphs/rmdh0s/rmdh1s n1 n2 rmgphl/rmdh0l/rmdh1l rmdls rmdll t we rmer (1) formula for rmgphs, rmdls, rmdh0s, and rmdh1s ? 2 ? n1 (2) formula for rmgphl, rmdll, rmdh0l, and rmdh1l + 1 + n2 (3) formula for rmer ? 1 t w : width of rin input waveform 1/f prs : width of internal operation clock cycle after division control by prsen a: tolerance (%) [ ] int : round down the fractional portion of the value produced by the formula in the brackets. n1, n2: variables of waveform change caused by noise note1 t we : end width of rin input note2 notes 1. set the values of n1 and n2 as required to meet the user s system specification. 2. this end width is counted after rmdll. the low-level width actually required after the last data has been received is as follows: (rmdll + 1 + rmer + 1) (width of internal operation clock cycle after division control by prsen) t w (1 ? a/100) 1/f prs int t w (1 + a/100) 1/f prs int t we (1 ? a/100) 1/f prs int www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 284 15.4.5 error interrupt generation timing after the guide pulse has been detected normally, the intrerr signal is generated under any of the following conditions. ? counter < rmdls at the rising edge of rin ? rmdll counter and counter after rmdll < rmer at the rising edge of rin ? counter < rmdh0s at the falling edge of rin ? rmdh0l counter < rmdh1s at the falling edge of rin ? register changes so that rmdh1l counter while rin is at high level the intrerr signal is not generated until the guide pulse is detected. once the intrerr signal has been generated, it will not be generated again until the next guide pulse is detected. the generation timing of the intrerr signal is shown in figure 15-7. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 285 figure 15-7. generation timing of intrerr signal rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr intrend rin intrerr rin intrerr example 1 counter < rmgphs intrerr is not generated. basic waveform example 2 rmgphl counter intrerr is not generated. example 3 counter < rmdls intrerr is generated. example 4 rmdll counter and counter < rmer intrerr is generated. example 5 rmdll counter and rmer counter intrerr is not generated. intrend is generated. example 6 counter < rmdh0s intrerr is generated. example 7 rmdh0l counter rmdh1s intrerr is generated. example 8 rmdh1l counter intrerr is generated. rmgphs rmgphl rmdls rmdll rmer rmdh1l rmdh0s rmdh1s rmdh0l www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 286 15.4.6 noise elimination this remote controller receiver provides a function that supplies the signals input from the outside to the rin pin after eliminating noise. noise width can be eliminated by setting bit 5 (prsen) and bit 6 (ncw) of the remote controller receive control register (rmcn) as shown in figure 15-2. table 15-2. noise elimination width prsen division control signal ncw noise elimination width control signal internal operation clock cycle after division control by prsen (1/f prs ) eliminatable noise width 00 1/f rem less than 1/f rem 01 1/f rem less than 2/f rem 10 2/f rem less than 2/f rem 11 2/f rem less than 4/f rem remark f rem : source clock of remote controller counter a noise elimination operation is performed by using the internal operation clock after division control by prsen. then, after the external input signal from rin pin has been synchronized with the clock, if ncw = 0, the signal after sampling is performed twice is processed as a rin input in the circuit. if ncw = 1, the signal after sampling is performed three times is processed as a rin input in the circuit. the following shows the flow of a noise elimination operation. <1> select whether or not the internal operation clock is divided by prsen. prsen = 0: not divided (f prs = f rem ) prsen = 1: divided (f prs = f rem /2) <2> synchronize the external input signal from the rin pin with the internal operation clock. <3> generate a signal (samp1) sampling the synchronized signal for the first time. (the signal is later than the synchronized signal by one clock.) <4> generate a signal (samp2) sampling the synchronized signal and samp1 for the second time. (when synchronized signal = samp1 = h, samp1 is latched.) <5> generate a signal (samp3) sampling the synchronized signal and samp2 for the third time. (when synchronized signal = samp2 = h, samp2 is latched.) <6> select a signal to be the rin input in the circuit using ncw. ncw = 0: samp2 is processed as the rin input in the circuit. ncw = 1: samp3 is processed as the rin input in the circuit. figure 15-8 shows an example of a noise elimination operation. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user ? s manual u15400ej3v0ud 287 figure 15-8. noise elimination operation example (1/2) (a) 1-clock noise elimination (prsen = 0, ncw = 0) remark internal rin is a signal after synchronization and sampling are performed twice, and is therefore later than the actual signal input from the outside to the rin pin by two to three clocks. (b) 2-clock noise elimination (prsen = 0, ncw = 1) remark internal rin is a signal after synchronization and sampling are performed three times, and is therefore later than the actual signal input from the outside to the rin pin by 3 to 4 clocks. clock clock rin (ideal) rin synchronization samp2 samp3 internal rin noise delayed by 3 to 4 clocks samp1 h h l h l l l since synchronized signal = samp1 = h, samp1 is latched from this point and later. since synchronized signal = samp2 = h is not satisfied, samp2 is not latched. clock rin (ideal) rin synchronization samp1 samp2 internal rin noise delayed by 2 to 3 clocks l h l l since synchronized signal = samp1 = h is not satisfied, samp1 is not latched. l www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 15 remote controller receiver user?s manual u15400ej3v0ud 288 figure 15-8. noise elimination operation example (2/2) (c) 2-clock noise elimination (prsen = 1, ncw = 0) remark internal rin is a signal after synchronization and sampling are performed twice, and is therefore later than the actual signal input from the outside to the rin pin by 4 to 6 clocks. (d) 4-clock noise elimination (prsen = 1, ncw = 1) remark internal rin is a signal after synchronization and sampling are performed three times, and is therefore later than the actual signal input from the outside to the rin pin by 6 to 8 clocks. clock divider rin (ideal) rin synchronization samp2 samp3 internal rin noise delayed by 6 to 8 clocks samp1 clock h h l h l l since synchronized signal = samp2 = h is not satisfied, samp2 is not latched. since synchronized signal = samp1 = h, samp1 is latched. l clock divider rin (ideal) rin synchronization samp2 internal rin noise delayed by 4 to 6 clocks samp1 clock l h l l since synchronized signal = samp1 = h is not satisfied, samp1 is not latched. l www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 289 chapter 16 interrupt functions 16.1 interrupt function types the following two types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupt this interrupt undergoes mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 16-1. a standby release signal is generated. for the pD789477, 789478, and 78f9478, 5 external and 16 internal interrupt sources are incorporated as maskable interrupts. for the pd789479 note and 78f9479 note , 6 external and 16 internal interrupt sources are incorporated as maskable interrupts. note under development 16.2 interrupt sources and configuration a total of 22 non-maskable and maskable interrupts are incorporated as interrupt sources for the pD789477, 789478, and 78f9478, and a total of 23 for the pd789479 and 78f9479. (see table 16-1 ). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user?s manual u15400ej3v0ud 290 table 16-1. interrupt sources interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable ? intwdt watchdog timer overflow (with watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (with interval timer mode selected) internal 0004h (b) 1 intp0 pin (intp0) input edge detection 0006h 2 intp1 pin (intp1) input edge detection 0008h 3 intp2 pin (intp2) input edge detection 000ah 4 intp3 pin (intp3) input edge detection external 000ch (c) 5 intrin remote controller edge detection 000eh intsr20 uart reception completion 6 intcsi20 end of 3-wire sio transfer for serial interface 20 0010h 7 intcsi10 end of 3-wire sio transfer for serial interface 1a0 0012h 8 intst20 end of uart transmission for serial interface 20 0014h 9 intwti standard time interval signal of watch timer (wt) 0016h 10 inttm20 match between tm20 and cr20 0018h 11 inttm50 match between tm50 and cr50 001ah 12 inttm60 match between tm60 and cr60 (in 8-bit counter mode), and between tm50, tm60 and cr50, cr60 (in 16-bit timer mode) 001ch 13 inttm61 match between tm61 and cr61 001eh 14 intad0 end of a/d conversion 0020h 15 intwt watch timer (wt) overflow internal 0022h (b) 16 intkr00 key return signal detection external 0024h (c) 17 intrerr remote controller reception error occurrence 0026h 18 intgp remote controller guide pulse detection 0028h 19 intrend remote controller data reception completion 002ah 20 intdfull read request for remote controller 8-bit shift data internal 002ch (b) maskable 21 intkr01 note 3 key return signal detection external 002eh (c) notes 1. default priority is the priority order when more than one maskable interrupt request is generated at the same time. 0 is the highest priority and 21 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 16-1. 3. pd789479 and 78f9479 only. remark only one of the two watchdog timer interrupt (intwdt) sources, non-maskable or maskable (internal), can be selected. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user?s manual u15400ej3v0ud 291 figure 16-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt intm0: external interrupt mode register 0 intm1: external interrupt mode register 1 krm00: key return mode register 00 krm01: key return mode register 01 if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag mk if ie internal bus intm0, intm1, krm00, krm01 interrupt request edge detector vector table address generator standby release signal www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 292 16.3 registers controlling interrupt function the following five types of registers are used to control the interrupt functions. ? interrupt request flag registers (if0 to if2) ? interrupt mask flag registers (mk0 to mk2) ? external interrupt mode registers (intm0 and intm1) ? program status word (psw) ? key return mode registers (krm00 and krm01) table 16-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 16-2. flags corresponding to interrupt request signal names interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intrin intsr20/intcsi20 intcsi10 intst20 intwti inttm20 inttm50 inttm60 inttm61 intad0 intwt intkr00 intrerr intgp intrend intdfull intkr01 note wdtif pif0 pif1 pif2 pif3 rinif srif20 csiif10 stif20 wtiif tmif20 tmif50 tmif60 tmif61 adif0 wtif krif00 rerrif gpif rendif dfullif krif01 note wdtmk pmk0 pmk1 pmk2 pmk3 rinmk srmk20 csimk10 stmk20 wtimk tmmk20 tmmk50 tmmk60 tmmk61 admk0 wtmk krmk00 rerrmk gpmk rendmk dfullmk krmk01 note note pd789479 and 78f9479 only www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 293 (1) interrupt request flag registers (if0 to if2) an interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. it is cleared (0) when the interrupt request is acknowledged, when the reset signal is input, or when an instruction is executed. if0 to if2 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 16-2. format of interrupt request flag registers symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w if0 csiif10 srif20 rinif pif3 pif2 pif1 pif0 wdtif ffe0h 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w if1 wtif adif0 tmif61 tmif60 tmif50 tmif20 wtiif stif20 ffe1h 00h r/w symbol 7 6 <5> <4> <3> <2> <1> <0> address after reset r/w if2 0 0 krif01 note dfullif rendif gpif rerrif krif00 ffe2h 00h r/w if interrupt request flag 0 no interrupt request signal generated 1 an interrupt request signal is generated and an interrupt request made note pd789479 and 78f9479 only cautions 1. the wdtif flag can be read/written only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. because p30 to p33 function alternately as external interrupts, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0 to pmk3) before using the port in output mode. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 294 (2) interrupt mask flag registers (mk0 to mk2) interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 to mk2 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. figure 16-3. format of interrupt mask flag registers symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w mk0 csimk10 srmk20 rinmk pmk3 pmk2 pmk1 pmk0 wdtmk ffe4h ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w mk1 wtmk admk0 tmmk61 tmmk60 tmmk50 tmmk20 wtimk stmk20 ffe5h ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> address after reset r/w mk2 1 1 krmk01 note dfullmk rendmk gpmk rerrmk krmk00 ffe6h ffh r/w mk interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note pd789479 and 78f9479 only cautions 1. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the wdtmk flag results in an undefined value being detected. 2. because p30 to p33 function alternately as external interrupts, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0 to pmk3) before using the port in output mode. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 295 (3) external interrupt mode registers (intm0, intm1) these registers are used to specify the valid edge for intp0 to intp3. intm0 and intm1 are set with an 8-bit memory manipulation instruction. reset input sets these registers to 00h. figure 16-4. format of external interrupt mode registers symbol 7 6 5 4 3 2 1 0 address after reset r/w intm0 es21 es20 es11 es10 es01 es00 0 0 ffech 00h r/w symbol 7 6 5 4 3 2 1 0 address after reset r/w intm1 0 0 0 0 0 0 es31 es30 ffedh 00h r/w esn1 esn0 intpn valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges remark n = 0, 1, 2, and 3 cautions 1. always set bits 0 and 1 of intm0, and 2 to 7 of intm1 to 0. 2. before setting intm0 and intm1, set (1) the interrupt mask flags (pmk0 to pmk3) to disable interrupts. to enable interrupts, clear (0) the interrupt request flags (pif0 to pif3), then clear (0) the interrupt mask flags (pmk0 to pmk3). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 296 (4) program status word (psw) the program status word is used to hold the instruction execution results and the current status of the interrupt requests. the ie flag, used to enable and disable maskable interrupts, is mapped to the psw. the psw can be read and written in 8-bit units, and can be manipulated by using bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt is acknowledged, the psw is automatically saved to the stack, and the ie flag is reset (0). reset input sets the psw to 02h. figure 16-5. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 used in the execution of ordinary instructions ie 0 1 disabled enabled interrupt acknowledgment enable/disable www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 297 (5) key return mode register 00 (krm00) this register is used to set the pin that is to detect the key return signal (falling edge of port 0). krm00 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 16-6. format of key return mode register 00 symbol 7 6 5 4 3 2 1 0 address after reset r/w krm00 krm007 krm006 krm005 krm004 0 0 0 krm000 fff5h 00h r/w krm000 control of key return signal detection 0 key return signal not detected 1 key return signal detected (p00 to p03 falling edge detection) krm00n control of key return signal detection 0 key return signal not detected 1 key return signal detected (p0n falling edge detection) remark n = 4 to 7 cautions 1. always set bits 1 to 3 to 0. 2. before setting krm00, set (1) bit 0 (krmk00) of mk2 to disable interrupts. to enable interrupts, clear (0) krmk00 after clearing (0) bit 0 (krif00) of if2. 3. on-chip pull-up resistors are not automatically connected in input mode even when key return signal detection is specified. therefore, when detecting the key return signal, connect the pull-up resistor of the corresponding bit using pull-up resistor option register b0 (pub0). although these resistors are disconnected when the mode changes to output, key return signal detection continues unchanged. figure 16-7. block diagram of falling edge detector notes 1. the pin names are p00/kr00 to p07/kr07 in the pd789479 and 78f9479. 2. for selecting the pin to be used as falling edge input. p00/kr0 p01/kr1 p02/kr2 p03/kr3 p04/kr4 p05/kr5 p06/kr6 p07/kr7 falling edge detector krmk00 intkr00 standby release signal key return mode register 00 (krm00) selector note 2 { note 1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 298 (6) key return mode register 01 (krm01) ( pd789479 and 78f9479 only) this register is used to set the pin that is to detect the key return signal (falling edge of port 6). krm01 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 16-8. format of key return mode register 01 symbol 7 6 5 4 3 2 1 0 address after reset r/w krm01 krm017 krm016 krm015 krm014 0 0 0 krm010 fff4h 00h r/w krm010 control of key return signal detection 0 key return signal not detected 1 key return signal detected (p60 to p63 falling edge detection) krm01n control of key return signal detection 0 key return signal not detected 1 key return signal detected (p6n falling edge detection) remark n = 4 to 7 cautions 1. always set bits 1 to 3 to 0. 2. before setting krm01, set (1) bit 5 (krmk01) of mk2 to disable interrupts. to enable interrupts, clear (0) krmk01 after clearing (0) bit 5 (krif01) of if2. 3. if any of the pins specified for key return signal detection is low level, the key return signal cannot be detected even if a falling edge is generated at other key return pins. 4. when even one of the p60/ani0/kr10/ to p67/ani7/kr17 pins is used as an a/d input, set krm010 and krm014 to krm017 to 0. figure 16-9. block diagram of falling edge detector notes for selecting the pin to be used as falling edge input. falling edge detector krmk01 intkr01 standby release signal key return mode register 01 (krm01) selector note 2 p60/ani0/kr10 p61/ani1/kr11 p62/ani2/kr12 p63/ani3/kr13 p64/ani4/kr14 p65/ani5/kr15 p66/ani6/kr16 p67/ani7/kr17 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 299 16.4 interrupt servicing operation 16.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector table are loaded the pc, and then program execution branches. figure 16-10 shows the flow from non-maskable interrupt request generation to acknowledgment, figure 16-11 shows the timing of non-maskable interrupt acknowledgment, and figure 16-12 shows the acknowledgment operation when a number of non-maskable interrupts are generated. caution during non-maskable interrupt service program execution, do not input another non-maskable interrupt request; if it is input, the service program will be interrupted and the new non- maskable interrupt request will be acknowledged. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 300 figure 16-10. flow from generation of non-maskable interrupt request to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing starts wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 16-11. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 16-12. non-maskable interrupt request acknowledgment second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 301 16.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vectored interrupt is acknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in table 16-3. refer to figures 16-14 and 16-15 for the timing of interrupt request acknowledgment. table 16-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated immediately before the bt or bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. a pending interrupt is acknowledged when the status in which it can be acknowledged is set. figure 16-13 shows the algorithm of interrupt request acknowledgment. when a maskable interrupt request is acknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servicing, use the reti instruction. figure 16-13. interrupt request acknowledgment program algorithm start if = 1? mk = 0? ie = 1? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) 1 f cpu www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 302 figure 16-14. interrupt request acknowledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt if the interrupt request has generated an interrupt request flag ( if) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n ? 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution. figure 16-14 shows an example using the 8-bit data transfer instruction mov a, r. because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of mov a, r. figure 16-15. interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execution) clock cpu nop mov a, r saving psw and pc, and jump to interrupt servicing interrupt servicing program interrupt 8 clocks if the interrupt request flag ( if) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after execution of the next instruction is complete. figure 16-15 shows an example whereby an interrupt request was generated in the 2nd clock of nop (a 2-clock instruction). in this case, the interrupt request will be processed after execution of mov a, r, which follows nop, is complete. caution when interrupt request flag registers (if0 to if2), or interrupt mask flag registers (mk0 to mk2) are being accessed, interrupt requests will be held pending. 16.4.3 multiple interrupt servicing multiple interrupt servicing, in which an interrupt request is acknowledged while another interrupt request being serviced, can be executed using the priority order. if multiple interrupts are generated at the same time, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to table 16-1 ). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 303 figure 16-16. example of multiple interrupt servicing example 1. acknowledging multiple interrupts intyy ei main servicing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is acknowledged during the servicing of interrupt intxx and multiple interrupt servicing is performed. before each interrupt request is acknowledged, the ei instruction is issued and the interrupt request is enabled. example 2. multiple interrupt servicing is not performed because interrupts are disabled intyy ei main servicing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupt requests are disabled (the ei instruction has not been issued) in the intxx interrupt servicing, the interrupt request intyy is not acknowledged and multiple interrupt servicing is not performed. intyy is held pending and is acknowledged after intxx servicing is completed. ie = 0: interrupt requests disabled www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 16 interrupt functions user ? s manual u15400ej3v0ud 304 16.4.4 putting interrupt requests on hold if an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. such instructions (interrupt request pending instructions) are as follows. ? instructions that manipulate interrupt request flag registers (if0 to if2) ? instructions that manipulate interrupt mask flag registers (mk0 to mk2) www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 305 chapter 17 standby function 17.1 standby function and configuration 17.1.1 standby function the standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) halt mode this mode is set when the halt instruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduce the power consumption as much as the stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is executed. the stop mode stops the main system clock oscillator and stops the entire system. the power consumption of the cpu can be substantially reduced in this mode. the data memory can be retained at a low voltage (v dd = 1.8 v). therefore, this mode is useful for retaining the contents of the data memory at extremely low power. the stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscillator stabilizes after the stop mode has been released. if processing must be resumed immediately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. in addition, the statuses of the output latches of the i/o ports and output buffers are also retained. caution to set the stop mode, be sure to stop the operations of the peripheral hardware, and then execute the stop instruction. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user?s manual u15400ej3v0ud 306 17.1.2 register controlling standby function the wait time after the stop mode is released upon interrupt request generation until oscillation stabilizes is controlled by the oscillation stabilization time selection register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 15 /f x , not 2 17 /f x , to stabilize oscillation after reset input. figure 17-1. format of oscillation stabilization time selection register osts2 0 0 1 00000 osts2 osts1 osts0 osts r/w fffah 04h r/w 76543210 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 setting prohibited symbol address after reset oscillation stabilization time selection other than above caution the wait time after the stop mode is released does not include the time from stop mode release to clock oscillation start (?a? in the figure below), regardless of whether stop mode is released by reset input or by interrupt generation. a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user ? s manual u15400ej3v0ud 307 17.2 standby function operation 17.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. the operation statuses in the halt mode are shown in the following table. table 17-1. operation statuses in halt mode halt mode operation status during main system clock operation halt mode operation status during sub system clock operation item subsystem clock operating subsystem clock stopped main system clock operating main system clock stopped clock generator oscillation enabled for both main system clock and sub system clock, but clock s upply to cpu is stopped subsystem clock 4 multiplication circuit operation stopped cpu operation stopped ports (output latches) status before halt mode setting retained 16-bit timer 20 operable operable note 1 8-bit timer 50 operable operable note 2 8-bit timer 60 operable operable note 3 8-bit timer 61 operable operable note 3 watch timer operable operable note 4 operable operable note 5 watchdog timer operable operation stopped key return circuit operable serial interface 20 operable operable note 6 serial interface 1a0 operable operable note 6 lcd controller/driver operable note 7 operable notes 4, 7 operable note 7 operable notes 5, 7 a/d converter operation stopped multiplier operation stopped remote controller receiver operable operable note 4 operable operable note 5 external interrupts operable note 8 notes 1. operation is enabled when the 24-bit counter mode is selected. 2. operation is enabled when either the subsystem clock or the input signal from timer 60 (when timer 60 is operable) is selected as the count clock. 3. operation is enabled only when the external input clock is selected as the count clock. 4. operation is enabled when the main system clock is selected. 5. operation is enabled when the subsystem clock is selected. 6. operation is enabled only when an external clock is selected. 7. the halt instruction can be set after display instruction execution. 8. operation is enabled only for a maskable interrupt that is not masked. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user ? s manual u15400ej3v0ud 308 (2) releasing halt mode the halt mode can be released by the following three sources. (a) release by unmasked interrupt request the halt mode is released by an unmasked interrupt request. in this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed. if interrupts are disabled, the instruction at the next address is executed. figure 17-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation remarks 1. the broken lines indicate the case where the interrupt request that released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt servicing is performed: 9 to 10 clocks ? when vectored interrupt servicing is not performed: 1 to 2 clocks (b) release by non-maskable interrupt request the halt mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user?s manual u15400ej3v0ud 309 (c) release by reset input when the halt mode is released by the reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. figure 17-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x : 6.55 ms) reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark f x : main system clock oscillation frequency table 17-2. operation after releasing halt mode releasing source mk ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 retains halt mode non-maskable interrupt request ? executes interrupt servicing reset input ?? reset processing : don ? t care caution some constraints apply when the flash version ( pd78f9478 and 78f9479) is used in the halt mode with the subclock multiplied by 4 as the cpu clock. for details, refer to 19.2 cautions on pd78f9478 and 78f9479. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user ? s manual u15400ej3v0ud 310 17.2.2 stop mode (1) setting and operation status of stop mode the stop mode is set by executing the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been executed, the wait time set by the oscillation stabilization time selection register (osts) elapses, and then the operation mode is set. the operation statuses in the stop mode are shown in the following table. table 17-3. operation statuses in stop mode stop mode operation status during main system clock operation item subsystem clock operating subsystem clock st opped main system clock oscillation st opped subsystem clock 4 multiplication circuit operation stopped cpu operation stopped ports (output latches) status before stop mode setting retained 16-bit timer 20 operation stopped 8-bit timer 50 operable note 1 operable note 2 8-bit timer 60 operable note 3 8-bit timer 61 operable note 3 watch timer operable note 4 operation stopped watchdog timer operation stopped key return circuit operable serial interface 20 operable note 5 serial interface 1a0 operable note 5 lcd controller/driver operable note 4 operation stopped a/d converter operation stopped multiplier operation stopped remote controller receiver operable note 4 operation stopped external interrupts operable note 6 notes 1. operation is enabled when either the subsystem clock or the input signal from the timer 60 (when timer 60 is operable) is selected as the count clock. 2. operation is enabled when the input signal from timer 60 (when timer 60 is operable) is selected as the count clock. 3. operation is enabled when the external input clock is selected as the count clock. 4. operation is enabled when the subsystem clock is selected. 5. operation is enabled only when an external clock is selected. 6. operation is enabled only for a maskable interrupt that is not masked www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user ? s manual u15400ej3v0ud 311 (2) releasing stop mode the stop mode can be released by the following two sources. (a) release by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. if interrupts are disabled, the instruction at the next address is executed. figure 17-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark the broken lines indicate the case where the interrupt request that released the standby mode is acknowledged. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 17 standby function user?s manual u15400ej3v0ud 312 (b) release by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 17-5. releasing stop mode by reset input remark f x : main system clock oscillation frequency table 17-4. operation after releasing stop mode releasing source mk ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 retains stop mode reset input ? - ? - reset processing : don?t care stop instruction reset signal wait (2 15 /f x : 6.55 ms) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 313 chapter 18 reset function the following two operations are available to generate reset signals. (1) external reset input by reset pin (2) internal reset by watchdog timer program loop time detection external and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 18-1. each pin is high impedance during reset input or during oscillation stabilization time just after reset release. when a high level is input to the reset pin, the reset is released and program execution is started after the oscillation stabilization time (2 15 /f x ) has elapsed. the reset applied by the watchdog timer overflow is automatically released after reset, and program execution is started after the oscillation stabilization time (2 15 /f x ) has elapsed (see figures 18-2 to 18-4 .) cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is released by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 18-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 18 r eset f unction user ? s manual u15400ej3v0ud 314 figure 18-2. reset timing by reset input x1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 18-3. reset timing by overflow in watchdog timer x1 overflow in watchdog timer internal reset signal port pin hi-z during normal operation reset period (oscillation continues) normal operation (reset processing) oscillation stabilization time wait figure 18-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin delay delay hi-z stop instruction execution during normal operation reset period (oscillation stops) stop status (oscillation stops) normal operation (reset processing) oscillation stabilization time wait www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 18 r eset f unction user ? s manual u15400ej3v0ud 315 table 18-1. status of hardware after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) set stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p3, p5, p8 note 3 ) (output latches) 00h port mode registers (pm0 to pm3, pm5, pm8 note 3 ) ffh port function registers (pf7, pf8) 00h pull-up resistor option registers (pub0 to pub3) 00h processor clock control register (pcc) 02h subclock oscillation mode register (sckm) 00h subclock selection register (ssck) retained note 4 subclock control register (css) 00h oscillation stabilization time selection register (osts) 04h timer counter (tm20) 0000h compare register (cr20) ffffh mode control register (tmc20) 00h 16-bit timer 20 capture register (tcp20) undefined timer counters (tm50, tm60, tm61) 00h compare registers (cr50, cr60, crh60, cr61, crh61) undefined mode control registers (tmc50, tmc60, tmc61) 00h 8-bit timer 50, 60, 61 carrier generator output control register (tca60) 00h mode control register (wtm) 00h watch timer interrupt time selection register (wtim) 00h clock selection register (wdcs) 00h watchdog timer mode register (wdtm) 00h operation mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface status register (asis20) 00h baud rate generator control register (brgc20) 00h transmit shift register (txs20) ffh serial interface 20 receive buffer register (rxb20) undefined notes 1. while a reset signal is being input, and during the oscillation stabilization period, only the contents of the pc will be undefined; the remainder of the hardware will be the same state as after reset. 2. in standby mode, ram enters the hold state after reset. 3. port 8 is used only when the port function is specified by a mask option or port function register (refer to chapter 20 mask options and 4.3 (3) port function registers ). 4. the register is set to 00h only by reset input. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 18 r eset f unction user ? s manual u15400ej3v0ud 316 table 18-1. status of hardware after reset (2/2) hardware status after reset operation mode register (csim1a0) 00h shift register (sio1a0) 00h buffer memory (sbmem0 to sbmemf) undefined automatic data transmit/receive control register (adtc0) 00h automatic data transmit/receive address pointer (adtp0) undefined serial interface 1a0 automatic data transmit/receive transfer interval specification register (adti0) 00h mode register (adml0, adml1) 00h input channel specification register (ads0) 00h a/d converter conversion result register (adcrl0) 00h display mode register (lcdm0) 00h lcd controller/driver clock control register (lcdc0) 00h 16-bit result storage register (mul0) undefined data register (mra0, mrb0) undefined multiplier control register (mulc0) 00h control register (rmcn) 00h data register (rmdr) 00h shift register reception counter register (rmscr) 00h shift register (rmsr) 00h compare registers (rmgphs, rmgphl, rmdls, rmdll, rmdh0s, rmdh0l, rmdh1s, rmdh1l) 00h remote controller receiver end width selection register (rmer) 00h request flag register (if0 to if2) 00h mask flag register (mk0 to mk2) ffh external interrupt mode register (intm0, intm1) 00h interrupts key return mode registers (krm00, krm01 note ) 00h note krm01 is only provided in the pd789479 and 78f9479 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 317 chapter 19 flash memory version the pd78f9478 is available as the flash memory version of the pD789477 and 789478 (mask rom versions). the pd78f9479 is available as the flash memory version of the pd789479 (mask rom version). the differences between the pd78f9478, 78f9479 and the mask rom versions are shown in table 19-1. table 19-1. differences between pd78f9478, 78f9479, and mask rom version flash memory version mask rom version item pd78f9478 pd78f9479 note pD789477 pd789478 pd789479 note rom 32 kb (flash memory) 48 kb (flash memory) 24 kb 32 kb 48 kb internal ram 1,024 bytes 1,536 bytes 768 bytes 1,024 bytes 1,536 bytes internal memory lcd display ram 28 4 bits pin function selection s16 to s27 (lcd segment output) or p70 to p73 and p80 to p87 (general- purpose ports) selectable by a port function register (pf7 and pf8) in bit units selectable by a mask option in bit units circuit to multiply subsystem clock by 4 use enabled/disabled by subclock select register (ssck) use enabled/disabled by a mask option pull-up resistor of port 5 none selectable by a mask option in 1-bit units key return signal detection pins p00/kr0 to p07/kr7 p00/kr00 to p07/kr07, p60/ani0/kr10 to p67/ani7/kr17 p00/kr0 to p07/kr7 p00/kr00 to p07/kr07, p60/ani0/ kr10 to p67/ani7/ kr17 restrictions in halt mode when using subclock 4 clock refer to 19.2 cautions on pd78f9478 and 78f9479 . none ic0 pin not provided provided v pp pin provided not provided electrical specifications refer to chapter 22 electrical specifications ( pD789477, 789478, 78f9478) and chapter 23 electrical specifications (target) ( pd789479, 78f9479) note under development caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user?s manual u15400ej3v0ud 318 19.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f9478 or 78f9479 mounted on the target system (on-board). a flash memory program adapter (fa adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products of naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontroller is solder-mounted on the target system. ? distinguishing software facilitates low-quantity, varied model production ? easy data adjustment when starting mass production 19.1.1 programming environment the following shows the environment required for pd78f9478 and 78f9479 flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals of flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 19-1. environment for writing program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9478 or pd78f9479 v pp v dd v ss reset 3-wire serial i/o or uart www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 319 19.1.2 communication mode use the communication mode shown in table 19-2 to perform communication between the dedicated flash programmer and pd78f9478 or pd78f9479. table 19-2. communication mode list type setting note 1 cpu clock communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses 3-wire serial i/o sio ch-0 (3-wired, sync.) si20/rxd20/p22 so20/txd20/p21 sck20/asck20/ p20 0 3-wire serial i/o with handshake sio ch-3 + handshake 100 hz to 1.25 mhz note 2 1, 2, 4, 5 mhz note 3 1 to 5 mhz note 2 1.0 si20/rxd20/p22 so20/txd20/p21 sck20/asck20/ p20 p11 (hs) 3 uart uart ch-0 (async.) 4,800 to 76,800 bps notes 2, 4 5 mhz note 5 4.91 or 5 mhz note 2 1.0 rxd20/si20/p22 txd20/so20/p21 8 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 22 electrical specifications ( pD789477, 789478, 78f9478) and chapter 23 electrical specifications (target) ( pd789479, 78f9479) . 3. only 2 mhz or 4 mhz can be selected for flashpro iii. 4. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew. 5. available for only flashpro iv. however, when using flashpro iii, be sure to select the clock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. figure 19-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 320 figure 19-3. example of connection with dedicated flash programmer (a) 3-wire serial i/o (b) 3-wire serial i/o with handshake (c) uart notes 1. connect the clk pin to the x1 pin, and separate it from the on-board resonator when the system clock is supplied from the dedicated flash programmer. do not connect to the clk pin when the clock of the on-board resonator is used. 2. when using uart with flashpro iii, the clock of the resonator connected to the x1 pin must be used, so do not connect the clk pin. caution the v dd pin, if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. before using the power supply connected to the v dd pin, supply voltage before starting programming. dedicated flash programmer vpp1 vdd reset sck so si clk note 1 gnd v pp v dd reset sck20 si20 so20 x1 v ss pd78f9478, 78f9479 dedicated flash programmer vpp1 vdd reset sck so si hs gnd v pp v dd reset sck20 si20 so20 p11 (hs) clk note 1 x1 v ss pd78f9478, 78f9479 dedicated flash programmer vpp1 vdd reset so si clk notes 1, 2 gnd v pp v dd reset r x d20 t x d20 x1 v ss pd78f9478, 78f9479 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 321 if flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, the following signals are generated for the pd78f9478 and 78f9479. for details, refer to the manual of flashpro iii/flashpro iv. table 19-3. pin connection list signal name i/o pin function pin name 3-wire serial i/o 3-wire serial i/o with handshake uart vpp1 output write voltage v pp vpp2 ?? ? vdd i/o v dd voltage generation/ voltage monitoring v dd note note note gnd ? ground v ss clk output clock output x1 reset output reset signal reset si input receive signal so20/txd20 so output transmit signal si20/rxd20 sck output transfer clock sck20 hs input handshake signal p11 (hs) note v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 322 19.1.3 on-board pin processing when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. in normal operation mode, input 0 v to the v pp pin. in flash memory programming mode, a write voltage of 10.0 v (typ.) is supplied to the v pp pin, so perform either of the following. (1) connect a pull-down resistor (rv pp = 10 k ? ) to the v pp pin. (2) use the jumper on the board to switch the v pp pin input to either the programmer or directly to gnd. a v pp pin connection example is shown below. figure 19-4. v pp pin connection example the following shows the pins used by the serial interface. serial interface pins used 3-wire serial i/o si20, so20, sck20 3-wire serial i/o with handshake si20, so20, sck20, p11 (hs) uart rxd20, txd20 when connecting the dedicated flash programmer to a serial interface pin that is connected to another device on- board, signal conflict or abnormal operation of the other device may occur. care must therefore be taken with such connections. pd78f9478, pd78f9479 v pp connection pin of dedicated flash programmer pull-down resistor (rv pp ) www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 323 (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection with the other device or set the other device to the output high impedance status. figure 19-5. signal conflict (input pin of serial interface) (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. to prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. figure 19-6. abnormal operation of other device input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. pd78f9478, pd78f9479 pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd78f9478 or 78f9479 affects another device in the flash memory programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f9478, pd78f9479 pd78f9478, pd78f9479 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 324 if the reset signal of the dedicated flash programmer is connected to the reset pin connected to the reset signal generator on-board, a signal conflict occurs. to prevent this, isolate the connection with the reset signal generator. if the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. therefore, do not input reset signals from other than the dedicated flash programmer. figure 19-7. signal conflict (reset pin) when the pd78f9478 enters the flash memory programming mode, all the pins other than those that communicate with flash programmer are in the same status as immediately after reset. if the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to v dd or v ss via a resistor. when using the on-board clock, connect x1, x2, xt1, and xt2 as required in the normal operation mode. when using the clock output of the flash programmer, connect it directly to x1, disconnecting the main resonator on-board, and leave the x2 pin open. the subsystem clock conforms to the normal operation mode. to use the power output from the flash programmer, connect the v dd pin to vdd of the flash programmer, and v ss pin to gnd of the flash programmer, respectively. to use the on-board power supply, make connection in accordance with the normal operation mode. however, because the voltage is monitored by the flash programmer, be sure to connect vdd of the flash programmer. supply the same power as in the normal operation mode to the other power pins (av dd and av ss ). process the other pins (s0 to s27, com0 to com3, v lc0 to v lc2 , caph, and capl) in the same manner as in the normal operation mode. reset connection pin of dedicated flash programmer reset signal generator signal conflict output pin the signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. pd78f9478, pd78f9479 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 325 19.1.4 connection of adapter for flash writing the following figure shows an example of recommended connection when the adapter for flash writing is used. figure 19-8. wiring example for flash writing adapter with 3-wire serial i/o pd78f9478 pd78f9479 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 326 figure 19-9. wiring example for flash writing adapter with 3-wire serial i/o with handshake pd78f9478 pd78f9479 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 327 figure 19-10. wiring example for flash writing adapter with uart pd78f9478 pd78f9479 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 19 flash memory version user ? s manual u15400ej3v0ud 328 19.2 cautions on pd78f9478 and 78f9479 (1) when using halt mode with subclock multiplied by four observe the following constraints when using the flash version ( pd78f9478 and 78f9479) in the halt mode with the subclock multiplied by 4 as the cpu clock. ? be sure to insert the following number of nop instructions immediately after the halt instruction. operating temperature number of nop instructions t a = ? 40 to +45 c2 t a = ? 40 to +80 c3 t a = ? 40 to +85 c4 ? save the value of the a register to the internal high-speed ram area before the halt instruction is executed (because the value of the a register may be changed when the halt mode is released). www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 329 chapter 20 mask options the pD789477, 789478, and 789479 have the following mask options. ? pin function the segment pins of the lcd and port 7 (input port) can be selected in 1-bit units. <1> s (16 + n) <2> p7n (n = 0 to 3) the segment pins of the lcd and port 8 (i/o port) can be selected in 1-bit units. <1> s (20 + m) <2> p8m (m = 0 to 7) ? subsystem clock 4 multiplication circuit the use of a circuit to multiply the subsystem clock (32.768 khz) by 4 (131 khz) is selected. <1> 4 multiplication circuit is used <2> 4 multiplication circuit is not used ? pull-up resistor the connection of on-chip pull-up resistors for port 5 (i/o port) can be switched in 1-bit units. <1> pull-up resistor is connected <2> pull-up resistor is not connected caution mask options are not provided for flash memory products ( pd78f9478 and 78f9479). www.datasheet.co.kr datasheet pdf - http://www..net/
330 user?s manual u15400ej3v0ud chapter 21 instruction set this chapter lists the instruction set of the pd789478 subseries. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 21.1 operation 21.1.1 operand identifiers and description methods operands are described in the ?operand? column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more description methods, select one of them. uppercase letters and the symbols #, !, $, and [ ] are keywords and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either functional names (x, a, c, etc.) or absolute names (names in parenthesis in the table below, r0, r1, r2, etc.) can be used for description. table 21-1. operand identifiers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 3-4 special function registers for symbols of special function registers. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 331 21.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by address or register contents in parenthesis x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) v: exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 21.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 x: set/cleared according to the result r: previously saved value is restored www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 332 21.2 operation list flag mnemonic operands bytes clocks operation zaccy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 24a r r, a note 1 24r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl+byte] 2 6 a (hl + byte) mov [hl+byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl+byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 333 flag mnemonic operands bytes clocks operation zaccy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 14rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl+byte] 2 6 a, cy a + (hl + byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl+byte] 2 6 a, cy a + (hl + byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl+byte] 2 6 a, cy a ? (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 334 flag mnemonic operands bytes clocks operation zaccy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl+byte] 2 6 a, cy a ? (hl + byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl+byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl+byte] 2 6 a a (hl + byte) a, #byte 2 4 a a v byte saddr, #byte 3 6 (saddr) (saddr) v byte a, r 2 4 a a v r a, saddr 2 4 a a v (saddr) a, !addr16 3 8 a a v (addr16) a, [hl] 1 6 a a v (hl) xor a, [hl+byte] 2 6 a a v (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 335 flag mnemonic operands bytes clocks operation zaccy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl+byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r24r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r24r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 336 flag mnemonic operands bytes clocks operation zaccy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 337 21.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+b y te] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc rmovmov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 338 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 21 instruction set user?s manual u15400ej3v0ud 339 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop www.datasheet.co.kr datasheet pdf - http://www..net/
340 user?s manual u15400ej3v0ud chapter 22 electrical specifications ( pD789477, 789478, 78f9478) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd power supply voltage av dd v dd = av dd ?0.3 to +6.5 v v pp pd78f9478 only note 1 ?0.3 to +10.5 v v i1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73 note 2 , p80 to p87 note 2 , x1, x2, xt1, xt2, reset ?0.3 to v dd + 0.3 note 3 v n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 on-chip pull-up resistor ?0.3 to v dd + 0.3 note 3 v p00 to p07, p10, p11, p20 to p25, p30 to p34, p50 to p53, p80 to p87 note 2 ?0.3 to v dd + 0.3 note 3 v output voltage v o s0 to s15, s16 to s27 note 2 , com0 to com3 ?0.3 to v lc0 + 0.3 v per pin ?10 ma output current, high i oh total for all pins ?30 ma per pin 30 ma output current, low i ol total for all pins 160 ma operating ambient temperature t a normal operation ?40 to +85 c flash memory programming 10 to 40 c storage temperature t stg pD789477, 789478 ?65 to +150 c pd78f9478 ?40 to +125 c (see the next page for a description of the notes.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user?s manual u15400ej3v0ud 341 notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 2. only when selected by a mask option or port function register 3. 6.5 v or less 1.8 v v dd 0 v 0 v v pp 1.8 v a b www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 342 main system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4ms oscillation frequency(f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 343 subsystem clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 crystal resonator xt2 xt1 ic0 (v pp ) c4 c3 r oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 344 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/4) parameter symbol conditions min. typ. max. unit per pin 10 ma output current, low i ol all pins 80 ma per pin ? 1ma output current, high i oh all pins ? 15 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 on-chip pull- up resistor note 1 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p00 to p07, p20 to p25, p30 to p34, p70 to p73 note 2 p80 to p87 note 2 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p00 to p07, p20 to p25, p30 to p34, p70 to p73 note 2 , p80 to p87 note 2 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh v dd = 1.8 to 5.5 v, i oh = ? 100 av dd ? 0.5 v 4.5 v dd 5.5 v, i ol = 10 ma 1.0 v v ol1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p80 to p87 note 2 1.8 v dd < 4.5 v, i ol = 400 a 0.5 v 4.5 v dd 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 1.8 v dd < 4.5 v, i ol = 1.6 ma 0.4 v notes 1. pD789477 and 789478 only 2. only when selected by a mask option or port function register remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 345 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/4) parameter symbol conditions min. typ. max. unit i lih1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73 note 1 , p80 to p87 note 1 , reset 3 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73 note 1 , p80 to p87 note 1 , reset ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ? 3 note 2 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ? 3 a software pull-up resistor r 1 v i = 0 v p00 to p07, p10, p11, p20 to p25, p30 to p34 50 100 200 k ? mask option pull-up resistor note 3 r 2 v i = 0 v p50 to p53 10 30 60 k ? notes 1. only when selected by a mask option or port function register 2. if there is no on-chip pull-up resistor for p50 to p53 (specified by a mask option) and if p50 to p53 have been set to input mode when a read instruction is executed to read from p50 to p53, a low-level input leakage current of up to ? 60 a flows during only one cycle. at all other times, the maximum leakage current is ? 3 a. 3. mask rom version only remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 346 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (3/4) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 23.5ma v dd = 3.0 v 10% note 3 0.4 1 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.2 0.5 ma v dd = 5.0 v 10% note 2 0.96 1.92 ma v dd = 3.0 v 10% note 3 0.26 0.76 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.1 0.34 ma v dd = 5.0 v 10% 33 67 a v dd = 3.0 v 10% 10 31 a 32.768 khz crystal oscillation operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 5 16 a v dd = 5.0 v 10% 130 200 a i dd3 32.768 khz crystal oscillation operation 4 multiplication operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 3.0 v 10% 50 110 a v dd = 5.0 v 10% 25 60 a v dd = 3.0 v 10% 8 28 a lcd not operating note 5 v dd = 2.0 v 10% 5 13 a v dd = 5.0 v 10% 27 66 a v dd = 3.0 v 10% 9.8 33 a 32.768 khz crystal oscillation halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 2.0 v 10% 6.6 17 a v dd = 5.0 v 10% 25 60 a lcd not operating note 5 v dd = 3.0 v 10% 8 28 a v dd = 5.0 v 10% 27 66 a i dd4 32.768 khz crystal oscillation 4 multiplication halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 3.0 v 10% 9.8 33 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5 a i dd5 stop mode note 5 v dd = 2.0 v 10% 0.05 3 a v dd = 5.0 v 10% note 2 35.2ma v dd = 3.0 v 10% note 3 1.1 2 ma power supply current note 1 ( pD789477, 789478) i dd6 5.0 mhz crystal oscillation a/d operating mode note 7 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.7 1.5 ma notes 1. the port current (including the current that flows to on-chip pull-up resistors) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system clock is stopped 5. when the lcd is not operating (lcdon0 = 0, lips0 = 0) 6. then the lcd is operating (lcdon0 = 1, lips0 = 1) 7. this is the total current that flows to v dd and av dd . remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 347 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (4/4) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 5.5 9.0 ma v dd = 3.0 v 10% note 3 1.3 2.3 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.8 1.6 ma v dd = 5.0 v 10% note 2 1.5 2.1 ma v dd = 3.0 v 10% note 3 0.41 0.85 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.2 0.43 ma v dd = 5.0 v 10% 115 200 a v dd = 3.0 v 10% 85 140 a 32.768 khz crystal oscillation operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 70 110 a v dd = 5.0 v 10% 315 480 a i dd3 32.768 khz crystal oscillation operation 4 multiplication operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 3.0 v 10% 200 300 a v dd = 5.0 v 10% 25 65 a v dd = 3.0 v 10% 7 29 a lcd not operating note 5 v dd = 2.0 v 10% 4 20 a v dd = 5.0 v 10% 27 71 a v dd = 3.0 v 10% 8.8 34 a 32.768 khz crystal oscillation halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 2.0 v 10% 5.6 24 a v dd = 5.0 v 10% 25 65 a lcd not operating note 5 v dd = 3.0 v 10% 7 29 a v dd = 5.0 v 10% 27 71 a i dd4 32.768 khz crystal oscillation 4 multiplication halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 3.0 v 10% 8.8 34 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5 a i dd5 stop mode note 5 v dd = 2.0 v 10% 0.05 3 a v dd = 5.0 v 10% note 2 6.5 10.2 ma v dd = 3.0 v 10% note 3 2.0 3.3 ma power supply current note 1 ( pd78f9477, 789478) i dd6 5.0 mhz crystal oscillation a/d operating mode note 7 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 1.3 2.6 ma notes 1. the port current (including the current that flows to on-chip pull-up resistors) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system clock is stopped 5. when the lcd is not operating (lcdon0 = 0, lips0 = 0) 6. then the lcd is operating (lcdon0 = 1, lips0 = 1) 7. this is the total current that flows to v dd and av dd . remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 348 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8.0 s operating with main system clock v dd = 1.8 to 5.5 v 1.6 8.0 s original oscillation operation v dd = 1.8 to 5.5 v 114 122 125 s cycle time (minimum instruction execution time) t cy operating with subsystem clock 4 multiplication operation v dd = 2.7 to 5.5 v 14.3 15.3 15.6 s capture input high-/low- level width t cpth , t cptl cpt20 10 s v dd = 2.7 to 5.5 v 0 4 mhz tmi60, tm61 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.125 s tmi60, tm61 input high-/low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high-/ low-level width t inth , t intl intp0 to intp3 10 s key return input low- level width t krl kr0 to kr7 10 s reset low-level width t rsl 10 s t cy vs. v dd (main system clock) power supply voltage v dd (v) cycle time t cy [ s] 123456 0.1 0.4 1.0 10 60 8.0 guaranteed operation range www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 349 (2) serial interface 20 (sio20) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low-level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sck20 to so20 output t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line. (b) 3-wire serial i/o mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low-level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck20 to so20 output t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 350 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 351 (3) serial interface 1a0 (sio1a0) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode, 3-wire serial i/o mode with automatic transmit/receive function (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy4 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy4 /2 ? 50 ns sck10 high-/low-level width t kh4 , t kl4 v dd = 1.8 to 5.5 v t kcy4 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si10 setup time (to sck10 ) t sik4 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 ) t ksi4 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sck10 to so10 output t kso4 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so10 output line. (b) 3-wire serial i/o mode, 3-wire serial i/o mode with automatic transmit/receive function (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy5 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck10 high-/low-level width t kh5 , t kl5 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si10 setup time (to sck10 ) t sik5 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 ) t ksi5 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck10 to so10 output t kso5 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so10 output line. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 352 ac timing measurement points (excluding x1 and xt1 inputs) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) capture input timing cpt20 t cptl t cpth tmi timing 1/f ti t til t tih tmi60, tmi61 interrupt input timing intp0 to intp3 t intl t inth key return input timing kr0 to kr7 t krl www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 353 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: remark m = 1, 2, 4, 5 uart mode (external clock input): t kcy3 t kl3 t kh3 asck20 t r t f t kcym t klm t khm sck10, sck20 t sikm t ksim t ksom input data output data si10, si20 so10, so20 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 354 8-bit a/d converter characteristics (t a = ?40 to +85 c, 1.8 v av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit av dd = 2.7 to 5.5 v 0.6 %fsr overall error note 1 av dd = 1.8 to 5.5 v 1.2 %fsr av dd = 2.7 to 5.5 v 14 100 s av dd = 1.8 to 5.5 v 28 100 s conversion time t conv when 4 subsystem clock is used (adsel1 = 1), av dd = 2.7 to 5.5 v 132 note 2 clock analog input voltage v ian 0av dd v notes 1. excludes quantization error ( 0.2%) 2. number of clocks of 4 subsystem clock remark fsr: full scale range lcd characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd output voltage differential note (common) v odc i o = 5 a0 0.2 v lcd output voltage differential note (segment) v ods i o = 1 a0 0.2 v note the voltage differential is the difference between the segment and common signal output ? s actual and ideal output voltages. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 355 data memory stop mode low supply voltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s data retention timing (stop mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt request signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request) oscillation stabilization wait time (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt note 2 s notes 1. use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). remark f x : main system clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 22 electrical specifications ( pD789477, 789478, 78f9478) user ? s manual u15400ej3v0ud 356 writing and erasing characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) ( pd78f9478 only) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz write operation frequency f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (at 5.0 mhz operation) 7ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 13 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 (at 5.0 mhz operation) 7ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s number of rewrites erase and write is considered as 1 cycle 20 times v pp0 normal operation 0 0.2v dd v v pp supply voltage v pp1 flash memory programming 9.7 10.0 10.3 v note excludes current flowing through ports (including on-chip pull-up resistors) www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 357 chapter 23 electrical specifications (target) ( pd789479, 78f9479) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd power supply voltage av dd v dd = av dd ?0.3 to +6.5 v v pp pd78f9479 only note 1 ?0.3 to +10.5 v v i1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73 note 2 , p80 to p87 note 2 , x1, x2, xt1, xt2, reset ?0.3 to v dd + 0.3 note 3 v n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 on-chip pull-up resistor ?0.3 to v dd + 0.3 note 3 v p00 to p07, p10, p11, p20 to p25, p30 to p34, p50 to p53, p80 to p87 note 2 ?0.3 to v dd + 0.3 note 3 v output voltage v o s0 to s15, s16 to s27 note 2 , com0 to com3 ?0.3 to v lc0 + 0.3 v per pin ?10 ma output current, high i oh total for all pins ?30 ma per pin 30 ma output current, low i ol total for all pins 160 ma operating ambient temperature t a normal operation ?40 to +85 c flash memory programming 10 to 40 c storage temperature t stg pd789479 ?65 to +150 c pd78f9479 ?40 to +125 c (see the next page for a description of the notes.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user?s manual u15400ej3v0ud 358 notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 2. only when selected by a mask option or port function register 3. 6.5 v or less 1.8 v v dd 0 v 0 v v pp 1.8 v a b www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 359 main system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4ms oscillation frequency(f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 360 subsystem clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 crystal resonator xt2 xt1 ic0 (v pp ) c4 c3 r oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 361 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/4) parameter symbol conditions min. typ. max. unit per pin 10 ma output current, low i ol all pins 80 ma per pin ? 1ma output current, high i oh all pins ? 15 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 on-chip pull- up resistor note 1 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p00 to p07, p20 to p25, p30 to p34, p70 to p73 note 2 p80 to p87 note 2 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p00 to p07, p20 to p25, p30 to p34, p70 to p73 note 2 , p80 to p87 note 2 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh v dd = 1.8 to 5.5 v, i oh = ? 100 av dd ? 0.5 v 4.5 v dd 5.5 v, i ol = 10 ma 1.0 v v ol1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p80 to p87 note 2 1.8 v dd < 4.5 v, i ol = 400 a 0.5 v 4.5 v dd 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 1.8 v dd < 4.5 v, i ol = 1.6 ma 0.4 v notes 1. pd789479 only 2. only when selected by a mask option or port function register remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 362 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/4) parameter symbol conditions min. typ. max. unit i lih1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73 note 1 , p80 to p87 note 1 , reset 3 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 p00 to p07, p10, p11, p20 to p25, p30 to p34, p60 to p67, p70 to p73 note 1 , p80 to p87 note 1 , reset ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ? 3 note 2 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ? 3 a software pull-up resistor r 1 v i = 0 v p00 to p07, p10, p11, p20 to p25, p30 to p34 50 100 200 k ? mask option pull-up resistor note 3 r 2 v i = 0 v p50 to p53 10 30 60 k ? notes 1. only when selected by a mask option or port function register 2. if there is no on-chip pull-up resistor for p50 to p53 (specified by a mask option) and if p50 to p53 have been set to input mode when a read instruction is executed to read from p50 to p53, a low-level input leakage current of up to ? 60 a flows during only one cycle. at all other times, the maximum leakage current is ? 3 a. 3. mask rom version only remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 363 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (3/4) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 2.5 5.0 ma v dd = 3.0 v 10% note 3 0.5 1.2 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.3 0.6 ma v dd = 5.0 v 10% note 2 1.0 2.0 ma v dd = 3.0 v 10% note 3 0.35 0.8 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.2 0.4 ma v dd = 5.0 v 10% 38 100 a v dd = 3.0 v 10% 13 50 a 32.768 khz crystal oscillation operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 7 25 a v dd = 5.0 v 10% 150 250 a i dd3 32.768 khz crystal oscillation operation 4 multiplication operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 3.0 v 10% 75 160 a v dd = 5.0 v 10% 25 70 a v dd = 3.0 v 10% 8 32 a lcd not operating note 5 v dd = 2.0 v 10% 5 15 a v dd = 5.0 v 10% 27 76 a v dd = 3.0 v 10% 9.8 37 a 32.768 khz crystal oscillation halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 2.0 v 10% 6.6 24 a v dd = 5.0 v 10% 25 70 a lcd not operating note 5 v dd = 3.0 v 10% 8 32 a v dd = 5.0 v 10% 27 76 a i dd4 32.768 khz crystal oscillation 4 multiplication halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 3.0 v 10% 9.8 37 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5 a i dd5 stop mode note 5 v dd = 2.0 v 10% 0.05 3 a v dd = 5.0 v 10% note 2 5.0 6.7 ma v dd = 3.0 v 10% note 3 1.5 2.2 ma power supply current note 1 ( pd789479) i dd6 5.0 mhz crystal oscillation a/d operating mode note 7 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.8 1.6 ma notes 1. the port current (including the current that flows to on-chip pull-up resistors) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system clock is stopped 5. when the lcd is not operating (lcdon0 = 0, lips0 = 0) 6. then the lcd is operating (lcdon0 = 1, lips0 = 1) 7. this is the total current that flows to v dd and av dd . remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 364 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (4/4) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 6.0 12.0 ma v dd = 3.0 v 10% note 3 1.6 3.2 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 1.0 2.5 ma v dd = 5.0 v 10% note 2 1.6 3.0 ma v dd = 3.0 v 10% note 3 0.5 1.2 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.3 0.6 ma v dd = 5.0 v 10% 130 250 a v dd = 3.0 v 10% 90 180 a 32.768 khz crystal oscillation operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 80 160 a v dd = 5.0 v 10% 330 550 a i dd3 32.768 khz crystal oscillation operation 4 multiplication operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 3.0 v 10% 250 400 a v dd = 5.0 v 10% 25 70 a v dd = 3.0 v 10% 8 32 a lcd not operating note 5 v dd = 2.0 v 10% 5 25 a v dd = 5.0 v 10% 27 76 a v dd = 3.0 v 10% 9.8 37 a 32.768 khz crystal oscillation halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 2.0 v 10% 6.6 24 a v dd = 5.0 v 10% 25 70 a lcd not operating note 5 v dd = 3.0 v 10% 8 32 a v dd = 5.0 v 10% 27 76 a i dd4 32.768 khz crystal oscillation 4 multiplication halt mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 6 v dd = 3.0 v 10% 9.8 37 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5 a i dd5 stop mode note 5 v dd = 2.0 v 10% 0.05 3 a v dd = 5.0 v 10% note 2 7.0 14.0 ma v dd = 3.0 v 10% note 3 2.3 4.2 ma power supply current note 1 ( pd78f9479) i dd6 5.0 mhz crystal oscillation a/d operating mode note 7 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 1.5 3.5 ma notes 1. the port current (including the current that flows to on-chip pull-up resistors) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system clock is stopped 5. when the lcd is not operating (lcdon0 = 0, lips0 = 0) 6. then the lcd is operating (lcdon0 = 1, lips0 = 1) 7. this is the total current that flows to v dd and av dd . remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 365 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8.0 s operating with main system clock v dd = 1.8 to 5.5 v 1.6 8.0 s original oscillation operation v dd = 1.8 to 5.5 v 114 122 125 s cycle time (minimum instruction execution time) t cy operating with subsystem clock 4 multiplication operation v dd = 2.7 to 5.5 v 14.3 15.3 15.6 s capture input high-/low- level width t cpth , t cptl cpt20 10 s v dd = 2.7 to 5.5 v 0 4 mhz tmi60, tm61 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.125 s tmi60, tm61 input high-/low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high-/ low-level width t inth , t intl intp0 to intp3 10 s key return input low- level width t krl kr00 to kr07, kr10 to kr17 10 s reset low-level width t rsl 10 s t cy vs. v dd (main system clock) power supply voltage v dd (v) cycle time t cy [ s] 123456 0.1 0.4 1.0 10 60 8.0 guaranteed operation range www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 366 (2) serial interface 20 (sio20) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low-level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sck20 to so20 output t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line. (b) 3-wire serial i/o mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low-level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck20 to so20 output t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 367 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 368 (3) serial interface 1a0 (sio1a0) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode, 3-wire serial i/o mode with automatic transmit/receive function (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy4 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy4 /2 ? 50 ns sck10 high-/low-level width t kh4 , t kl4 v dd = 1.8 to 5.5 v t kcy4 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si10 setup time (to sck10 ) t sik4 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 ) t ksi4 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sck10 to so10 output t kso4 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so10 output line. (b) 3-wire serial i/o mode, 3-wire serial i/o mode with automatic transmit/receive function (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy5 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck10 high-/low-level width t kh5 , t kl5 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si10 setup time (to sck10 ) t sik5 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 ) t ksi5 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck10 to so10 output t kso5 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the so10 output line. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 369 ac timing measurement points (excluding x1 and xt1 inputs) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) capture input timing cpt20 t cptl t cpth tmi timing 1/f ti t til t tih tmi60, tmi61 interrupt input timing intp0 to intp3 t intl t inth key return input timing kr00 to kr07, kr10 to kr17 t krl www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 370 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: remark m = 1, 2, 4, 5 uart mode (external clock input): t kcy3 t kl3 t kh3 asck20 t r t f t kcym t klm t khm sck10, sck20 t sikm t ksim t ksom input data output data si10, si20 so10, so20 www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 371 8-bit a/d converter characteristics (t a = ?40 to +85 c, 1.8 v av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit av dd = 2.7 to 5.5 v 0.6 %fsr overall error note 1 av dd = 1.8 to 5.5 v 1.2 %fsr av dd = 2.7 to 5.5 v 14 100 s av dd = 1.8 to 5.5 v 28 100 s conversion time t conv when 4 subsystem clock is used (adsel1 = 1), av dd = 2.7 to 5.5 v 132 note 2 clock analog input voltage v ian 0av dd v notes 1. excludes quantization error ( 0.2%) 2. number of clocks of 4 subsystem clock remark fsr: full scale range lcd characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd output voltage differential note (common) v odc i o = 5 a0 0.2 v lcd output voltage differential note (segment) v ods i o = 1 a0 0.2 v note the voltage differential is the difference between the segment and common signal output ? s actual and ideal output voltages. www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 372 data memory stop mode low supply voltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s data retention timing (stop mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt request signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request) oscillation stabilization wait time (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt note 2 s notes 1. use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). remark f x : main system clock oscillation frequency www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 23 electrical specifications (target) ( pd789479, 78f9479) user ? s manual u15400ej3v0ud 373 writing and erasing characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) ( pd78f9479 only) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz write operation frequency f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (at 5.0 mhz operation) 7ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 13 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 (at 5.0 mhz operation) 7ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s number of rewrites erase and write is considered as 1 cycle 20 times v pp0 normal operation 0 0.2v dd v v pp supply voltage v pp1 flash memory programming 9.7 10.0 10.3 v note excludes current flowing through ports (including on-chip pull-up resistors) www.datasheet.co.kr datasheet pdf - http://www..net/
374 user?s manual u15400ej3v0ud chapter 24 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h www.datasheet.co.kr datasheet pdf - http://www..net/
chapter 24 package drawings user ? s manual u15400ej3v0ud 375 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f1.25 14.0 0.2 b 12.0 0.2 m n0.08 0.145 0.05 p q0.1 0.05 1.0 j 0.5 (t.p.) k l0.5 1.0 0.2 i0.08 s1.1 0.1 r 3 + 4 ? 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t0.25 u0.6 0.15 www.datasheet.co.kr datasheet pdf - http://www..net/
376 user?s manual u15400ej3v0ud chapter 25 recommended soldering conditions the pD789477, 789478, and 78f9478 note should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) note the pd789479 and 78f9479 are under development and have therefore not been evaluated. table 25-1. surface mounting type soldering conditions pD789477gc- -8bt: 80-pin plastic qfp (14 14) pd789478gc- -8bt: 80-pin plastic qfp (14 14) pd78f9478gc-8bt: 80-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: twice or less vp15-00-2 wave soldering solder bath temperature: 260c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together (except for partial heating). www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 377 appendix a development tools the following development tools are available for development of systems using the pd789478 subseries. figure a-1 shows development tools. ? support for pc98-nx series unless specified otherwise, the products supported by ibm pc/at? compatibles can be used in the pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. ? windows unless specified otherwise, ?windows? indicates the following operating systems. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt? ver.4.0 www.datasheet.co.kr datasheet pdf - http://www..net/
appendix a development tools 378 user?s manual u15400ej3v0ud figure a-1. development tools notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is used only in the windows environment. language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit software package control software project manager (windows version only) note 2 software package flash memory writing environment www.datasheet.co.kr datasheet pdf - http://www..net/
appendix a development tools user ? s manual u15400ej3v0ud 379 a.1 software package software tools for development of the 78k/0s series are combined in this package. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, and device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the os used s sp78k0s host machine os supply medium ab17 japanese windows cd-rom bb17 pc-9800 series, ibm pc/at compatibles english windows a.2 language processing software program that converts program written in mnemonic into object codes that can be executed by a microcontroller. in addition, automatic functions to generate symbol tables and optimize branch instructions are also provided. used in combination with a device file (df789488) (sold separately). the assembler package is a dos-based application but may be used in the windows environment by using the project manager of windows (included in the assembler package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into object codes that can be executed by a microcontroller. used in combination with an assembler package (ra78k0s) and device file (df789488) (both sold separately). the c compiler package is a dos-based application but may be used in the windows environment by using the project manager of windows (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing information inherent to the device. used in combination with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789488 note 1 device file part number: s df789488 source file of functions for generating the object library included in c compiler package. necessary for changing the object library included in the c compiler package according to the customer ? s specifications. since this is a source file, its working environment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789488 is a common file that can be used with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s). www.datasheet.co.kr datasheet pdf - http://www..net/
appendix a development tools user ? s manual u15400ej3v0ud 380 remark in the part number differs depending on the host machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatible english windows cd-rom 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df789488 s cc78k0s-l host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 pc-9800 series, ibm pc/at compatible japanese windows 3p16 hp9000 series 700 hp-ux tm (rel. 10.10) dat 3k13 3.5" 2hd fd 3k15 sparcstation sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager control software created for efficient development of the user program in the windows environment. user program development operations such as editor startup, build, and debugger startup can be performed from the project manager. the project manager is included in the assembler package (ra78k0s). the project manager is used only in the windows environment. a.4 flash memory writing tools flashpro iii (fl-pr3, pg-fp3) flashpro iv (fl-pr4, pg-fp4) flash programmer dedicated flash programmer for microcontrollers incorporating flash memory fa-80gc-8bt fa-80gk-9eu flash memory writing adapter adapter for writing to flash memory and connected to flashpro iii. ? fa-80gc-8bt: for 80-pin plastic qfp (gc-8bt type) ? fa-80gk-9eu: for 80-pin plastic tqfp (gk-9eu type) remark the fl-pr3, fl-pr4, fa-80gc-8bt, and fa-80gk-9eu are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). www.datasheet.co.kr datasheet pdf - http://www..net/
appendix a development tools user ? s manual u15400ej3v0ud 381 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of an application system using the 78k/0s series. can be used with the integrated debugger id78k0s-ns. used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator the ie-78k0s-ns-a provides a coverage function in addition to the ie-78k0s-ns functions, thus enhancing the debug functions, including the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from ac 100 to 240 v outlet. ie-70000-98-if-c interface adapter adapter necessary when using a pc-9800 series pc (except notebook type) as the host machine (c bus supported) ie-70000-cd-if-a pc card interface pc card and interface cable necessary when using a notebook pc as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter interface adapter necessary when using an ibm pc/at compatible as the host machine (isa bus supported) ie-70000-pci-if-a interface adapter adapter necessary when using a personal computer incorporating a pci bus as the host machine ie-789488-ns-em1 emulation board board for emulating the peripheral hardware inherent to the device. used in combination with in-circuit emulator. np-80gc emulation probe cable to connect the in-circuit emulator and target system. used in combination with the ev-9200gc-80. ev-9200gc-80 conversion socket conversion socket to connect the np-80gc and a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted. np-80gc-tq np-h80gc-tq emulation probe cable to connect an in-circuit emulator to the target system. used in combination with the tgc- 080sbp. tgc-080sbp conversion adapter conversion adapter to connect the np-80gc-tq or np-h80gc-tq to a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted. np-80gk np-h80gk-tq emulation probe cable to connect an in-circuit emulator to the target system. used in combination with the tgk- 080sdw. tgk-080sdw conversion adapter conversion adapter to connect the np-80gk or np-h80gk-tq to a target system board on which an 80-pin plastic tqfp (fine pitch) (gk-9eu type) can be mounted. remarks 1. the np-80gc, np-80gc-tq, np-h80gc-tq, np-80gk, and np-h80gk-tq are products of naito densei machida mfg. co., ltd. (tel +81-45-475-4191). 2. the tgc-080sbp and tgk-080sdw are products of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) www.datasheet.co.kr datasheet pdf - http://www..net/
appendix a development tools user ? s manual u15400ej3v0ud 382 a.6 debugging tools (software) this debugger supports the in-circuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-ns is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. used in combination with a device file (df789488) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. the sm78k0s is wi ndows-based software. it can be used to debug the target system at c source level or assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, the development efficiency can be enhanced and the software quality can be improved. used in combination with a device file (df789488) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing information inherent to the device. used in combination with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789488 note device file part number: s df789488 note df789488 is a common file that can be used with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the operating system and supply medium to be used. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5" 2hd fd ab17 japanese windows bb17 pc-9800 series ibm pc/at compatibles english windows cd-rom www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 383 appendix b notes on target system design figures b-1 to b-6 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. of the products described in this chapter, the np-80gc, np-80gc-tq, np-h80gc-tq, np-80gk and np- h80gk-tq are products of naito densei machida mfg. co., ltd, and the tgc-080sbp and tgk-080sdw are products of tokyo eletech corporation. (1) np-80gc, np-80gc-tq, np-h80gc-tq figure b-1. distance between in-circuit emulator and conversion socket (80gc) note when np-h80gc-tq is used, the distance is 370 mm. 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789488-ns-em1 conversion socket: ev-9200gc-80 or conversion adapter: tgc-080sbp target system cn1 emulation probe np-80gc, np-80gc-tq np-h80gc-tq www.datasheet.co.kr datasheet pdf - http://www..net/
appendix b notes on target system design user ? s manual u15400ej3v0ud 384 figure b-2. connection conditions of target system (when np-80gc-tq is used) figure b-3. connection conditions of target system (when np-h80gc-tq is used) emulation probe np-80gc-tq emulation board ie-789488-ns-em1 24.8 mm 25 mm 40 mm 34 mm target system conversion adapter tgc-080sbp 21 mm 21 mm 11 mm emulation probe np-h80gc-tq emulation board ie-789488-ns-em1 25.3 mm 25 mm 42 mm 45 mm target system conversion adapter tgc-080sbp 21 mm 21 mm 11 mm www.datasheet.co.kr datasheet pdf - http://www..net/
appendix b notes on target system design user ? s manual u15400ej3v0ud 385 (2) np-80gk, np-h80gk-tq figure b-4. distance between in-circuit emulator and conversion adapter (80gk) note when np-h80gk-tq is used, the distance is 370 mm. 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789488-ns-em1 conversion adapter tgk-080sdw target system cn1 emulation probe np-80gk, np-h80gk-tq www.datasheet.co.kr datasheet pdf - http://www..net/
appendix b notes on target system design user ? s manual u15400ej3v0ud 386 figure b-5. connection conditions of target system (when np-80gk is used) figure b-6. connection conditions of target system (when np-h80gk-tq is used) emulation probe np-80gk emulation board ie-789488-ns-em1 24.8 mm 25 mm 40 mm 34 mm target system conversion adapter tgk-080sdw 18 mm 18 mm 11 mm emulation probe np-h80gk-tq emulation board ie-789488-ns-em1 25.3 mm 25 mm 42 mm 45 mm target system conversion adapter tgk-080sdw 18 mm 18 mm 11 mm www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 387 appendix c register index c.1 register index (register names in alphabetic order) [a] a/d conversion result register 0 (adcrl0) ...................................................................................... ..........................174 a/d converter mode register 0 (adml0).......................................................................................... ...........................176 a/d converter mode register 1 (adml1).......................................................................................... ...........................177 analog input channel specification register 0 (ads0)........................................................................... ......................178 asynchronous serial interface mode register 20 (asim20) ........................................................................ ................192 asynchronous serial interface status register 20 (asis20) ...................................................................... ..................194 automatic data transmit/receive address pointer 0 (adtp0)...................................................................... ................219 automatic data transmit/receive control register 0 (adtc0)..................................................................... ..................222 automatic data transmit/receive interval specification register 0 (adti0) ...................................................... ............223 [b] baud rate generator control register 20 (brgc20) ............................................................................... .....................195 [c] carrier generator output control register 60 (tca60) ........................................................................... ......................131 [e] 8-bit compare register 50 (cr50) ............................................................................................... ................................126 8-bit compare register 60 (cr60) ............................................................................................... ................................126 8-bit compare register 61 (cr61) ............................................................................................... ................................127 8-bit h width compare register 60 (crh60)...................................................................................... ..........................126 8-bit h width compare register 61 (crh61)...................................................................................... ..........................126 8-bit timer counter 50 (tm50) .................................................................................................. ...................................127 8-bit timer counter 60 (tm60) .................................................................................................. ...................................127 8-bit timer counter 61 (tm61) .................................................................................................. ...................................127 8-bit timer mode control register 50 (tmc50) ................................................................................... ..........................128 8-bit timer mode control register 60 (tmc60) ................................................................................... ..........................129 8-bit timer mode control register 61 (tmc61) ................................................................................... ..........................132 external interrupt mode register 0 (intm0) ..................................................................................... ...........................295 external interrupt mode register 1 (intm1) ..................................................................................... ...........................295 [i] interrupt mask flag register 0 (mk0) ........................................................................................... ................................294 interrupt mask flag register 1 (mk1) ........................................................................................... ................................294 interrupt mask flag register 2 (mk2) ........................................................................................... ................................294 interrupt request flag register 0 (if0) ........................................................................................ ..................................293 interrupt request flag register 1 (if1) ........................................................................................ ..................................293 interrupt request flag register 2 (if2) ........................................................................................ ..................................293 www.datasheet.co.kr datasheet pdf - http://www..net/
appendix c register index 388 user?s manual u15400ej3v0ud [k] key return mode register 00 (krm00) ............................................................................................ ........................... 297 key return mode register 01 (krm01) ............................................................................................ ........................... 298 [l] lcd clock control register 0 (lcdc0)........................................................................................... ............................. 255 lcd display mode register 0 (lcdm0) ............................................................................................ .......................... 254 [m] multiplication data register a0 (mra0)......................................................................................... .............................. 266 multiplication data register b0 (mrb0)......................................................................................... .............................. 266 multiplier control register 0 (mulc0) .......................................................................................... ............................... 268 [o] oscillation stabilization time selection register (osts) ....................................................................... ...................... 306 [p] port 0 (p0).................................................................................................................... ................................................ 77 port 1 (p1).................................................................................................................... ................................................ 78 port 2 (p2).................................................................................................................... ................................................ 79 port 3 (p3).................................................................................................................... ................................................ 84 port 5 (p5).................................................................................................................... ................................................ 86 port 6 (p6).................................................................................................................... ................................................ 87 port 7 (p7).................................................................................................................... ................................................ 89 port 8 (p8).................................................................................................................... ................................................ 90 port function register 7 (pf7)................................................................................................. ...................................... 93 port function register 8 (pf8)................................................................................................. ...................................... 93 port mode register 0 (pm0)..................................................................................................... ..................................... 91 port mode register 1 (pm1)..................................................................................................... ..................................... 91 port mode register 2 (pm2)..................................................................................................... ..................................... 91 port mode register 3 (pm3)..................................................................................................... ..................... 91, 112, 133 port mode register 5 (pm5)..................................................................................................... ..................................... 91 port mode register 8 (pm8)..................................................................................................... ..................................... 91 processor clock control register (pcc)......................................................................................... ............................... 98 pull-up resistor option register b0 (pub0) ..................................................................................... .............................. 93 pull-up resistor option register b1 (pub1) ..................................................................................... .............................. 93 pull-up resistor option register b2 (pub2) ..................................................................................... .............................. 93 pull-up resistor option register b3 (pub3) ..................................................................................... .............................. 93 [r] receive buffer register 20 (rxb20) ............................................................................................. .............................. 190 remote controller receive control register (rmcn) .............................................................................. ..................... 276 remote controller receive data register (rmdr) ................................................................................. ...................... 272 remote controller receive dh0l compare register (rmdh0l) ....................................................................... ........... 274 remote controller receive dh0s compare register (rmdh0s) ....................................................................... .......... 274 remote controller receive dh1l compare register (rmdh1l) ....................................................................... ........... 274 remote controller receive dh1s compare register (rmdh1s) ....................................................................... .......... 274 remote controller receive dll compare register (rmdll) ......................................................................... .............. 273 www.datasheet.co.kr datasheet pdf - http://www..net/
appendix c register index user?s manual u15400ej3v0ud 389 remote controller dls compare register (rmdls)................................................................................. ...................273 remote controller receive end-width select register (rmer) ..................................................................... ................275 remote controller receive gphl compare register (rmgphl)....................................................................... ...........273 remote controller receive gphs compare register (rmgphs)....................................................................... ..........273 remote control receive shift register (rmsr) ................................................................................... .........................271 remote controller shift register receive counter register (rmscr).............................................................. ..............272 [s] 16-bit capture register 20 (tcp20) ............................................................................................. ................................109 16-bit compare register 20 (cr20) .............................................................................................. ...............................109 16-bit multiplication result storage register h (mul0h) ........................................................................ ......................266 16-bit multiplication result storage register l (mul0l) ........................................................................ .......................266 16-bit timer counter 20 (tm20) ................................................................................................. ..................................109 16-bit timer mode control register 20 (tmc20) .................................................................................. .........................110 serial i/o shift register 1a0 (sio1a0) ......................................................................................... ................................219 serial operation mode register 1a0 (csim1a0)................................................................................... .......................220 serial operation mode register 20 (csim20) ..................................................................................... .........................191 subclock control register (css)................................................................................................ ..................................100 subclock oscillation mode register (sckm)...................................................................................... ............................99 subclock selection register (ssck)............................................................................................. ...............................100 [t] transmit shift register 20 (txs20)............................................................................................. .................................190 [w] watch timer interrupt time selection register (wtim)........................................................................... .......................164 watch timer mode control register (wtm) ........................................................................................ ..........................163 watchdog timer clock selection register (wdcs)................................................................................. ......................169 watchdog timer mode register (wdtm) ............................................................................................ .........................170 www.datasheet.co.kr datasheet pdf - http://www..net/
appendix c register index 390 user?s manual u15400ej3v0ud c.2 register index (register symbols in alphabetic order) [a] adcrl0: a/d conversion result register 0 ........................................................................................ ..................... 174 adml0: a/d converter mode register 0 ............................................................................................ ................... 176 adml1: a/d converter mode register 1 ............................................................................................ ................... 177 ads0: analog input channel specification register 0............................................................................. ............ 178 adtc0: automatic data transmit/receive control register 0 ....................................................................... .......... 222 adti0: automatic data transmit/receive interval specification register 0 ........................................................ ... 223 adtp0: automatic data transmit/receive address pointer 0 ........................................................................ ........ 219 asim20: asynchronous serial interface mode register 20 .......................................................................... .......... 192 asis20: asynchronous serial interface status register 20 ........................................................................ ........... 194 [b] brgc20: baud rate generator control register 20................................................................................. ................. 195 [c] cr20: 16-bit compare register 20 ................................................................................................ ..................... 109 cr50: 8-bit compare register 50 ................................................................................................. ...................... 126 cr60: 8-bit compare register 60 ................................................................................................ ....................... 126 cr61: 8-bit compare register 61 ................................................................................................ ....................... 127 crh60: 8-bit h width compare register 60 ....................................................................................... ................... 126 crh61: 8-bit h width compare register 61 ....................................................................................... ................... 126 csim1a0: serial operation mode register 1a0.................................................................................... .................... 220 csim20: serial operation mode register 20 ...................................................................................... .................... 191 css: subclock control register................................................................................................. ....................... 100 [i] if0: interrupt request flag register 0 ......................................................................................... ..................... 293 if1: interrupt request flag register 1 ......................................................................................... ..................... 293 if2: interrupt request flag register 2 ......................................................................................... ..................... 293 intm0: external interrupt mode register 0 ...................................................................................... .................... 295 intm1: external interrupt mode register 1 ...................................................................................... .................... 295 [k] krm00: key return mode register 00............................................................................................. ...................... 297 krm01: key return mode register 01............................................................................................. ...................... 298 [l] lcdc0: lcd clock control register 0 ............................................................................................ ....................... 255 lcdm0: lcd display mode register 0 ............................................................................................. ..................... 254 [m] mk0: interrupt mask flag register 0............................................................................................ ...................... 294 mk1: interrupt mask flag register 1............................................................................................ ...................... 294 mk2: interrupt mask flag register 2............................................................................................ ...................... 294 mra0: multiplication data register a0 .......................................................................................... ...................... 266 mrb0: multiplication data register b0 .......................................................................................... ...................... 266 www.datasheet.co.kr datasheet pdf - http://www..net/
appendix c register index user?s manual u15400ej3v0ud 391 mul0h: 16-bit multiplication result storage register h......................................................................... .................266 mul0l: 16-bit multiplication result storage register l ......................................................................... .................266 mulc0: multiplier control register 0........................................................................................... ...........................268 [o] osts: oscillation stabilization time selection register........................................................................ ................306 [p] p0: port 0 ..................................................................................................................... ...................................77 p1: port 1 ..................................................................................................................... ...................................78 p2: port 2 ..................................................................................................................... ...................................79 p3: port 3 ...................................................................................................................... ..................................84 p5: port 5 ...................................................................................................................... ..................................86 p6: port 6 ...................................................................................................................... ..................................87 p7: port 7 ...................................................................................................................... ..................................89 p8: port 8 ...................................................................................................................... ..................................90 pcc: processor clock control register.......................................................................................... ......................98 pf7: port function register 7.................................................................................................. ............................93 pf8: port function register 8.................................................................................................. ............................93 pm0: port mode register 0...................................................................................................... ............................91 pm1: port mode register 1...................................................................................................... ............................91 pm2: port mode register 2...................................................................................................... ............................91 pm3: port mode register 3...................................................................................................... ............91, 112, 133 pm5: port mode register 5...................................................................................................... ............................91 pm8: port mode register 8...................................................................................................... ............................93 pub0: pull-up resistor option register b0...................................................................................... .......................93 pub1: pull-up resistor option register b1...................................................................................... .......................93 pub2: pull-up resistor option register b2...................................................................................... .......................93 pub3: pull-up resistor option register b3...................................................................................... .......................93 [r] rmcn: remote controller receive control register ............................................................................... ...............276 rmdh0l: remote controller receive dh0l compare register ........................................................................ .........274 rmdh0s: remote controller receive dh0s compare register........................................................................ .........274 rmdh1l: remote controller receive dh1l compare register ........................................................................ .........274 rmdh1s: remote controller receive dh1s compare register........................................................................ .........274 rmdll: remote controller receive dll compare register.......................................................................... ..........273 rmdls: remote controller dls compare register.................................................................................. ..............273 rmdr: remote controller receive data register .................................................................................. ................272 rmer: remote controller receive end-width select register ...................................................................... .........275 rmgphl: remote controller receive gphl compare register ........................................................................ ........273 rmgphs: remote controller receive gphs compare register ........................................................................ ........273 rmscr: remote controller shift register receive counter register ............................................................... .........272 rmsr: remote control receive shift register .................................................................................... ..................271 rxb20: receive buffer register 20.............................................................................................. .........................190 [s] sckm: subclock oscillation mode register....................................................................................... .....................99 www.datasheet.co.kr datasheet pdf - http://www..net/
appendix c register index 392 user?s manual u15400ej3v0ud sio1a0: serial i/o shift register 1a0 .......................................................................................... .......................... 219 ssck: subclock selection register .............................................................................................. ...................... 100 [t] tca60: carrier generator output control register 60 ............................................................................ ............... 131 tcp20: 16-bit capture register 20 .............................................................................................. ......................... 109 tm20: 16-bit timer counter 20 .................................................................................................. ......................... 109 tm50: 8-bit timer counter 50 ................................................................................................... .......................... 127 tm60: 8-bit timer counter 60 ................................................................................................... .......................... 127 tm61: 8-bit timer counter 61 ................................................................................................... .......................... 127 tmc20: 16-bit timer mode control register 20................................................................................... ................... 110 tmc50: 8-bit timer mode control register 50.................................................................................... .................... 128 tmc60: 8-bit timer mode control register 60.................................................................................... .................... 129 tmc61: 8-bit timer mode control register 61.................................................................................... .................... 132 txs20: transmit shift register 20.............................................................................................. .......................... 190 [w] wdcs: watchdog timer clock selection register.................................................................................. ............... 169 wdtm: watchdog timer mode register ............................................................................................. .................. 170 wtim: watch timer interrupt time selection register ............................................................................ .............. 164 wtm: watch timer mode control register ......................................................................................... ................ 163 www.datasheet.co.kr datasheet pdf - http://www..net/
user?s manual u15400ej3v0ud 393 appendix d revision history the following table shows the revision history up to this edition. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/2) edition major revision from previous edition applied to: addition of pd789478 throughout change of v pp pin handling chapter 2 pin functions addition of figure 3-2 memory map ( pd789478) and figure 3-5 data memory addressing ( pd789478) chapter 3 cpu architecture change of block diagrams of p23 and p24 chapter 4 port functions addition of note on feedback resistor chapter 5 clock generator modification of description on 6.4.1 operation as timer interrupt and 6.4.2 operation as timer output chapter 6 16-bit timer 20 correction of bit name of bit 0 of timer mode control registers 60 and 61 (tmc60, tmc61) addition of caution on carrier generator output control register 60 (tca60) correction of values in table 7-8 square-wave output range of timer 61 chapter 7 8-bit timers 50, 60, and 61 addition of 10.5 (8) input impedance of ani0 to ani7 pins chapter 10 10-bit a/d converter modification of figure 11-1 block diagram of serial interface 20 modification of description on pe20 flag in figure 11-5 format of asynchronous serial interface status register 20 addition of description on uart receive data read chapter 11 serial interface 20 change of figure 13-2 lcd controller/driver block diagram chapter 13 lcd controller/driver revision of contents about flash memory programming as 19.1 flash memory characteristics chapter 19 pd78f9478 addition of electrical specifications chapter 21 electrical specifications addition of package drawings chapter 23 package drawings addition of recommended soldering conditions chapter 24 recommended soldering conditions revision of development tools deletion of description on embedded software appendix a development tools 2nd addition of revision history appendix c revision history www.datasheet.co.kr datasheet pdf - http://www..net/
appendix d revision history user?s manual u15400ej3v0ud 394 (2/2) edition major revision from previous edition applied to: addition of pd789479 and 78f9479 addition of 80-pin plastic tqfp (fine pitch) (12 12) throughout update of series lineup diagram in 1.5 78k/0s series lineup chapter 1 general addition of table 3-3 internal high-speed ram, internal low-speed ram capacity chapter 3 cpu architecture modification of description of minimum instruction execution time in figure 5-3. format of processor clock control register and figure 5-5. format of subclock control register addition of 5.4.6 subsystem clock 4 multiplication circuit chapter 5 clock generator addition of 6.5 cautions on using 16-bit timer 20 chapter 6 16-bit timer 20 modification of figure 13-2 lcd controller/driver block diagram addition of 13.8 examples of lcd drive power connections chapter 13 lcd controller/driver addition of description of key return mode register 01 (krm01) chapter 16 interrupt functions modification of description of cpu clock in table 19-2 communication mode list change of description of note 1 in figure 19-3 example of connection with dedicated flash programmer chapter 19 flash memory version addition of chapter chapter 23 electrical specifications (target) ( pd789479, 78f9479) addition of flashpro iv and fa-80gk-9eu to a.4 flash memory writing tools modification of a.5 debugging tools (hardware) appendix a development tools 3rd addition of appendix appendix b notes on target system design www.datasheet.co.kr datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of D789477

	To Download D789477 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .